參數(shù)資料
型號(hào)： ICS8430DYI-11
元件分類： 時(shí)鐘產(chǎn)生/分配
英文描述： 700 MHz, OTHER CLOCK GENERATOR, PQFP32
封裝： 7 X 7 MM, 1.40 MM HEIGHT, MS-026, LQFP-32
文件頁(yè)數(shù)： 16/16頁(yè)
文件大?。?/td> 179K
代理商： ICS8430DYI-11
8430DYI-11
www.icst.com/products/hiperclocks.html
REV. A FEBRUARY 10, 2003
9
Integrated
Circuit
Systems, Inc.
ICS8430I-11
700MHZ, LOW JITTER
LVCMOS-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminat-
ing resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed to
FIGURE 4B. LVPECL OUTPUT TERMINATION
3.3V
F
OUT
F
IN
5
2 Zo
Z
o
5
2
Z
o
3
2
Z
o
3
2
Z
o = 50
Z
o = 50
FIGURE 4A. LVPECL OUTPUT TERMINATION
RTT =
1
(V
OH + VOL / VCC –2) –2
Z
o
Z
o = 50
Z
o = 50
50
50
RTT
V
CC - 2V
F
IN
F
OUT
drive 50
transmission lines. Matched impedance techniques
should be used to maximize operating frequency and minimize
signal distortion.
Figures 4A and 4B show two different layouts
which are recommended only as guidelines. Other suitable clock
layouts may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
TERMINATION FOR LVPECL OUTPUTS
The schematic of the ICS8430I-11 layout example used in this lay-
out guideline is shown in
Figure 5A. The ICS8430I-11 recommended
PCB board layout for this example is shown in
Figure 5B. This
layout example is used as a general guideline. The layout in the
LAYOUT GUIDELINE
FIGURE 5A. SCHEMATIC OF RECOMMENDED LAYOUT
TL2
Zo = 50 Ohm
X1
R1
125
Termination
B (Not shown
in the layout)
S_LOAD
U1
8430-01
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
32
31
30
29
28
27
26
25
M5
M6
M7
M8
N0
N1
N2
GND
TEST
VCC
FO
UT1
nF
O
U
T
1
VCCO
FO
UT0
nF
O
U
T
0
GND
MR
S_CLOCK
S_DATA
S_LOAD
VCCA
nXTAL_SEL
REF_IN
XTAL1
M4
M3
M2
M1
M0
VCO_
SEL
nP
_LO
A
D
XTAL
2
IN-
R1
50
VDD
FO
UTN
C15
0.1u
TEST
S_CLOCK
C11
0.01u
S_DATA
R7
10
C14
0.1u
FO
UT
VDD
R3
125
VDD
R4
84
IN+
Termination A
IN-
TL1
Zo = 50 Ohm
R2
50
MR
REF_IN
C16
22u
R3
50
VDD
R2
84
IN+
XTAL_SEL
actual system will depend on the selected component types, the
density of the components, the density of the traces, and the stack
up of the P.C. board.
相關(guān)PDF資料
PDF描述
ICS8430DYI-11LFT 700 MHz, OTHER CLOCK GENERATOR, PQFP32
ICS8430DYI-11LF 700 MHz, OTHER CLOCK GENERATOR, PQFP32
ICS8430EY-11LFT 700 MHz, OTHER CLOCK GENERATOR, PQFP32
ICS8430EY-11LF 700 MHz, OTHER CLOCK GENERATOR, PQFP32
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