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參數(shù)資料
| 型號： | ICS8430AY-62LFT |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 12/23頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SYNTHESIZER LVPECL 32-LQFP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 系列： | HiPerClockS™ |
| 類型： | 頻率合成器 |
| PLL： | 帶旁路 |
| 輸入： | LVCMOS，LVTTL，晶體 |
| 輸出： | LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:2 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 500MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-LQFP |
| 供應(yīng)商設(shè)備封裝： | 32-TQFP（7x7） |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 8430AY-62LFT |
ICS8430-62 Datasheet
500MHz CRYSTAL-TO-3.3V, 2.5V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
ICS8430AY-62 REVISION A JULY 2, 2009
2
2009 Integrated Device Technology, Inc.
Functional Description
NOTE: The functional description that follows describes operation
using a 16MHz crystal. Valid PLL loop divider values for different
crystal or input frequencies are defined in the Input Frequency
Characteristics, Table 5, NOTE 1.
The ICS8430-62 features a fully integrated PLL and therefore
requires no external components for setting the loop bandwidth. A
parallel-resonant, fundamental crystal is used as the input to the
on-chip oscillator. The output of the oscillator is divided by 16 prior to
the phase detector. With a 16MHz crystal, this provides a 1MHz
reference frequency. The VCO of the PLL operates over a range of
250MHz to 500MHz. The output of the M divider is also applied to the
phase detector.
The phase detector and the M divider force the VCO output
frequency to be M times the reference frequency by adjusting the
VCO control voltage. Note that for some values of M (either too high
or too low), the PLL will not achieve lock. The output of the VCO is
scaled by a divider prior to being sent to each of the LVPECL output
buffers. The divider provides a 50% output duty cycle.
The programmable features of the ICS8430-62 support two input
modes to program the M divider and N output divider. The two input
operational modes are parallel and serial. Figure 1 shows the timing
diagram for each mode. In parallel mode, the nP_LOAD input is
initially LOW. The data on inputs M0 through M8 and N0 through N2
is passed directly to the M divider and N output divider. On the
LOW-to-HIGH transition of the nP_LOAD input, the data is latched
and the M divider remains loaded until the next LOW transition on
nP_LOAD or until a serial event occurs. As a result, the M and N bits
can be hard-wired to set the M divider and N output divider to a
specific default state that will automatically occur during power-up.
The TEST output is LOW when operating in the parallel input mode.
The relationship between the VCO frequency, the crystal frequency
and the M divider is defined as follows:
fVCO = fXTAL x M
16
The M value and the required values of M0 through M8 are shown in
Table 3B, Programmable VCO Frequency Function Table. Valid M
values for which the PLL will achieve lock for a 16MHz reference are
defined as 250
≤ M ≤ 500. The frequency out is defined as follows:
fout = fVCO = fXTAL x M
N16
N
Serial operation occurs when nP_LOAD is HIGH and S_LOAD is
LOW. The shift register is loaded by sampling the S_DATA bits with
the rising edge of S_CLOCK. The contents of the shift register are
loaded into the M divider and N output divider when S_LOAD
transitions from LOW-to-HIGH. The M divide and N output divide
values are latched on the HIGH-to-LOW transition of S_LOAD. If
S_LOAD is held HIGH, data at the S_DATA input is passed directly to
the M divider and N output divider on each rising edge of S_CLOCK.
The serial mode can be used to program the M and N bits and test
bits T1 and T0. The internal registers T0 and T1 determine the state
of the TEST output as follows:
T1
T0
TEST Output
00
LOW
0
1
S_DATA, Shift Register Input
1
0
Output of M Divider
1
Do Not Use
Time
SERIAL LOADING
PARALLEL LOADING
t
S
t
H
t
S
t
H
t
S
M, N
M0
M1
M2
M3
M4
M5
M6
M7
M8
N0
N1
N2
T0
T1
S_CLOCK
S_DATA
S_LOAD
nP_LOAD
M0:M8, N0:N2
nP_LOAD
Figure 1. Parallel & Serial Load Operations
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| ICS8430AYI-61 | 制造商:ICS 制造商全稱:ICS 功能描述:500MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER |
| ICS8430AYI-61LF | 功能描述:IC SYNTHESIZER LVPECL 32-LQFP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:HiPerClockS™ 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
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| ICS8430AYI-61T | 制造商:ICS 制造商全稱:ICS 功能描述:500MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER |
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