參數(shù)資料
型號: ICS843081AGI-01T
元件分類: 時(shí)鐘產(chǎn)生/分配
英文描述: 700 MHz, OTHER CLOCK GENERATOR, PDSO8
封裝: 4.40 X 3 MM, 0.925 MM HEIGHT, MO-153, TSSOP-8
文件頁數(shù): 3/15頁
文件大?。?/td> 397K
代理商: ICS843081AGI-01T
843081AGI-01
www.icst.com/products/hiperclocks.html
REV. B JANUARY 23, 2006
11
Integrated
Circuit
Systems, Inc.
ICS843081I-01
FEMTOCLOCKSCRYSTAL-TO-
3.3V, 2.5V LVPECL CLOCK MULTIPLIER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 5.
To calculate worst case power dissipation into the load, use the following equations which assume a 50
Ω load, and a termination
voltage of V
CC
- 2V.
For logic high, V
OUT
= V
OH_MAX
= V
CC_MAX
– 0.9V
(V
CCO_MAX
- V
OH_MAX
) = 0.9V
For logic low, V
OUT
= V
OL_MAX
= V
CC_MAX
– 1.7V
(V
CCO_MAX
- V
OL_MAX
) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V
OH_MAX
– (V
CC_MAX
- 2V))/R
L
] * (V
CC_MAX
- V
OH_MAX
) = [(2V - (V
CC_MAX
- V
OH_MAX
))/R
L
] * (V
CC_MAX
- V
OH_MAX
) =
[(2V - 0.9V)/50
Ω] * 0.9V = 19.8mW
Pd_L = [(V
OL_MAX
– (V
CC_MAX
- 2V))/R
L
] * (V
CC_MAX
- V
OL_MAX
) = [(2V - (V
CC_MAX
- V
OL_MAX
))/R
L
] * (V
CC_MAX
- V
OL_MAX
) =
[(2V - 1.7V)/50
Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
FIGURE 5. LVPECL DRIVER CIRCUIT AND TERMINATION
Q1
V
OUT
V
CC
RL
50
V
CC - 2V
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