ICS843051AG REVISION A OCTOBER 13, 2010
11
2010 Integrated Device Technology, Inc.
ICS843051 Data Sheet
FEMTOCLOCK CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR
Schematic Example
Figure 5A shows a schematic example of the ICS843051. An
example of LVEPCL termination is shown in this schematic.
Additional LVPECL termination approaches are shown in the
LVPECL Termination Application Note. In this example, an 18pF
parallel resonant crystal is used. The C1 = 27pF and C2 = 33pF are
recommended for frequency accuracy. The C1 and C2 values may be
slightly adjusted for optimizing frequency accuracy.
Figure 5A. ICS843051 Schematic Example
PC Board Layout Example
Figure 5B shows an example of ICS843051 P.C. board layout. The
crystal X1 footprint shown in this example allows installation of either
surface mount HC49S or through-hole HC49 package. The footprints
of other components in this example are listed in the Table 6. There
should be at least one decoupling capacitor per power pin. The
decoupling capacitors should be located as close as possible to the
power pins. The layout assumes that the board has clean analog
power ground plane.
Figure 5B. ICS843051 PC Board Layout Example
Table 6. Footprint Table
NOTE: Table 6 lists component sizes shown in this layout example.
R4
82.5
R1
1K
C4
0.01u
VCC
+
-
VCC
Zo = 50 Ohm
R6
82.5
C1
27pF
C3
10uF
1 8 p F
Zo = 50 Ohm
C2
33pF
R2
10
VCC
R3
133
U1
ICS843051i
1
2
3
4
8
7
6
5
VCCA
VEE
XTAL_OUT
XTAL_IN
VCC
Q0
nQ0
FREQ_SEL
C5
0.1u
Q
VCCA
R5
133
VCC
nQ
X1
19.44MHz
Reference
Size
C1, C2
0402
C3
0805
C4, C5
0603
R2
0603