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參數(shù)資料
| 型號： | ICS843034AYT |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 750 MHz, OTHER CLOCK GENERATOR, PQFP48 |
| 封裝： | 7 X 7 MM, 1.40 MM HEIGHT, MS-026BBC, LQFP-48 |
| 文件頁數(shù)： | 18/24頁 |
| 文件大?。?/td> | 726K |
| 代理商： | ICS843034AYT |
IDT / ICS 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
3
ICS843034AY REV B JULY 18, 2006
ICS843034
FEMTOCOCKS MULTI-RATE 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
PRELIMINARY
specific default state that will automatically occur during power-
up. The TEST output is LOW when operating in the parallel input
mode. The relationship between the VCO frequency, the crystal
frequency and the M divider is defined as follows:
The M value and the required values of M0 through M8 are
shown in Table 3B to program the VCO Frequency Function
Table. Valid M values for which the PLL will achieve lock for a
25MHz reference are defined as 23
≤ M ≤ 30. The frequency
out is defined as follows:
Serial operation occurs when nP_LOAD is HIGH and S_LOAD
is LOW. The shift register is loaded by sampling the S_DATA
bits with the rising edge of S_CLOCK. The contents of the shift
register are loaded into the M divider and Nx output divider
when S_LOAD transitions from LOW-to-HIGH. The M divide
and Nx output divide values are latched on the HIGH-to-LOW
transition of S_LOAD. If S_LOAD is held HIGH, data at the
S_DATA input is passed directly to the M divider and Nx output
divider on each rising edge of S_CLOCK. The serial mode can
be used to program the M and Nx bits and test bits T1 and T0.
The internal registers T0 and T1 determine the state of the
TEST output as follows:
FUNCTIONAL DESCRIPTION
NOTE: The functional description that follows describes opera-
tion using a 25MHz crystal. Valid PLL loop divider values for
different crystal or input frequencies are defined in the Input
Frequency Characteristics, Table 5, NOTE 1.
The ICS843034 features a fully integrated PLL and therefore
requires no external components for setting the loop bandwidth.
A fundamental crystal is used as the input to the on-chip oscil-
lator. The output of the oscillator is fed into the phase detector.
A 25MHz crystal provides a 25MHz phase detector reference
frequency. The VCO of the PLL operates over a range of 560MHz
to 750MHz. The output of the M divider is also applied to the
phase detector.
The phase detector and the M divider force the VCO output
frequency to be M times the reference frequency by adjusting
the VCO control voltage. Note that for some values of M (either
too high or too low), the PLL will not achieve lock. The output of
the VCO is scaled by a divider prior to being sent to each of the
LVPECL output buffers. The divider provides a 50% output duty
cycle.
The ICS843034 supports either serial or parallel programming
modes to program the M feedback divider and N output divider.
Figure 1 shows the timing diagram for each mode. In parallel
mode, the nP_LOAD input is initially LOW. The data on the M,
NA, and NB inputs are passed directly to the M divider and
both N output dividers. On the LOW-to-HIGH transition of the
nP_LOAD input, the data is latched and the M and N dividers
remain loaded until the next LOW transition on nP_LOAD or
until a serial event occurs. As a result, the M and Nx bits can
be hardwired to set the M divider and Nx output divider to a
T1
T0
TEST Output
00
LOW
0
1
S_Data, Shift Register Output
1
0
Output of M divider
1
FOUTA0 same frequency
fVCO = fxtal x M
FOUT = fVCO = fxtal x M
N
FIGURE 1. PARALLEL & SERIAL LOAD OPERATIONS
T 1
T0
NB2
NB1
NB0
NA2
NA1
NA0
M8
M7
M6
M5
M4
M3
M2
M1
M 0
S_CLOCK
S_DATA
S_LOAD
nP_LOAD
M0:M8, NA0:NA2, NB0:NB2
nP_LOAD
S_LOAD
SERIAL LOADING
PARALLEL LOADING
M, N
t
S
t
S
t
H
t
S
t
H
Time
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