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參數(shù)資料
| 型號(hào)： | ICS843020AY-01LFT |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 6/21頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SYNTHESIZER LVPECL 32-LQFP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 系列： | HiPerClockS™, FemtoClock™ |
| 類型： | 頻率合成器 |
| PLL： | 帶旁路 |
| 輸入： | 晶體 |
| 輸出： | LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:2 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 680MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-LQFP |
| 供應(yīng)商設(shè)備封裝： | 32-TQFP（7x7） |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 843020AY-01LFT |
843020AY-01
www.idt.com
REV. C JULY 26, 2010
14
ICS843020-01
FEMTOCLOCKS 680MHZ, CRYSTAL-TO-
3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
FIGURE 5B. PCB BOARD LAYOUT FOR ICS843020-01
The following component footprints are used in this layout
example:
All the resistors and capacitors are size 0603.
POWER AND GROUNDING
Place the decoupling capacitors C14 and C15, as close as pos-
sible to the power pins. If space allows, placement of the
decoupling capacitor on the component side is preferred. This
can reduce unwanted inductance between the decoupling ca-
pacitor and the power pin caused by the via.
Maximize the power and ground pad sizes and number of vias
capacitors. This can reduce the inductance between the power
and ground planes and the component power and ground pins.
The RC filter consisting of R7, C11, and C16 should be placed
as close to the V
CCA pin as possible.
CLOCK TRACES AND TERMINATION
Poor signal integrity can degrade the system performance or
cause system failure. In synchronous high-speed digital systems,
the clock signal is less tolerant to poor signal integrity than other
signals. Any ringing on the rising or falling edge or excessive ring
back can cause system failure. The shape of the trace and the
trace delay might be restricted by the available space on the board
and the component location. While routing the traces, the clock
signal traces should be routed first and should be locked prior to
routing other signal traces.
The differential 50
Ω output traces should have the
same length.
Avoid sharp angles on the clock trace. Sharp angle
turns cause the characteristic impedance to change on
the transmission lines.
Keep the clock traces on the same layer. Whenever pos-
sible, avoid placing vias on the clock traces. Placement
of vias on the traces can affect the trace characteristic
impedance and hence degrade signal integrity.
To prevent cross talk, avoid routing other signal traces in
parallel with the clock traces. If running parallel traces is
unavoidable, allow a separation of at least three trace
widths between the differential clock trace and the other
signal trace.
Make sure no other signal traces are routed between the
clock trace pair.
The matching termination resistors should be located as
close to the receiver input pins as possible.
CRYSTAL
The crystal X1 should be located as close as possible to the pins
25 (XTAL_IN) and 24 (XTAL_OUT). The trace length between the
X1 and U1 should be kept to a minimum to avoid unwanted para-
sitic inductance and capacitance. Other signal traces should not
be routed near the crystal traces.
TL1, TL21N are 50 Ohm
traces and equal length
R2
VIA
T
L1N
GND
C15
R4
TL1
R1
TL
1
X1
VCC
C11
PIN 1
C1
C14
TL1N
C2
R3
C16
R7
Close to the input
pins of the
receiver
U1
VCCA
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS843020AY-01T | 制造商:ICS 制造商全稱:ICS 功能描述:FEMTOCLOCKS-TM 680MHZ, CRYSTAL-TO- 3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER |
| ICS843021 | 制造商:ICS 制造商全稱:ICS 功能描述:FEMTOCLOCKS-TM CRYSTAL-TO- 3.3V LVPECL CLOCK GENERATOR |
| ICS843021AG | 制造商:ICS 制造商全稱:ICS 功能描述:FEMTOCLOCKS-TM CRYSTAL-TO- 3.3V LVPECL CLOCK GENERATOR |
| ICS843021AG-01 | 制造商:Integrated Device Technology Inc 功能描述:IC SYNTHESIZER LVPECL 8TSSOP |
| ICS843021AG-01T | 制造商:Integrated Device Technology Inc 功能描述:IC SYNTHESIZER LVPECL 8TSSOP |
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