
ICS843004AGI REVISION A FEBRUARY 19, 2010
13
2010 Integrated Device Technology, Inc.
ICS843004I Data Sheet
FEMTOCLOCK LVCMOS/CRYSTAL-TO-3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
Layout Guideline
Figure 6 shows a schematic example of the ICS843004I. An example
of LVEPCL termination is shown in this schematic. Additional
LVPECL termination approaches are shown in the LVPECL
Termination Application Note. In this example, an 18pF parallel
resonant 26.5625MHz crystal is used. The C1= 27pF and C2 = 33pF
are recommended for frequency accuracy. For different board layout,
the C1 and C2 may be slightly adjusted for optimizing frequency
accuracy.
Figure 6. ICS843004I Schematic Example
VCC=3.3V
C3
10uF
+
-
VCCO=3.3V
R3
133
To Logic
Input
pins
3.3V
VCC
Zo = 50 Ohm
Set Logic
Input to
'0'
C7
0.1u
3.3V
RD2
1K
VCC
VDD
VC
C
R10
82.5
R4
82.5
VCCA
Logic Control Input Examples
VDD
C2
33pF
C4
0.01u
+
-
Zo = 50 Ohm
RD1
Not Install
Zo = 50 Ohm
RU2
Not Install
R7
133
R8
82.5
C9
0.1u
C1
27pF
Set Logic
Input to
'1'
R9
133
X1
26.5625MHz
R2
10
1 8 p F
To Logic
Input
pins
Zo = 50 Ohm
VCCO
R6
82.5
C6
0.1u
U1
ICS843004
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
nQ
1
Q1
VC
C
O
Q0
nQ
0
MR
nP
LL
_S
EL
NC
VC
C
A
F_
S
E
L
0
VC
C
F_
S
E
L
1
XT
A
L
_O
U
T
XT
AL
_I
N
VE
E
T
E
ST
_C
LK
nX
T
A
L
_SE
L
VC
C
VE
E
nQ
3
Q3
VC
C
O
Q2
nQ
2
C8
0.1u
R5
133
RU1
1K
VC
C
O