參數(shù)資料
型號(hào): ICS843003AGLFT
廠商: IDT, Integrated Device Technology Inc
文件頁(yè)數(shù): 18/21頁(yè)
文件大小: 0K
描述: IC SYNTHESIZER LVPECL 24-TSSOP
標(biāo)準(zhǔn)包裝: 2,500
系列: HiPerClockS™, FemtoClock™
類型: 頻率合成器
PLL: 帶旁路
輸入: 晶體
輸出: LVPECL
電路數(shù): 1
比率 - 輸入:輸出: 1:3
差分 - 輸入:輸出: 無(wú)/是
頻率 - 最大: 700MHz
除法器/乘法器: 是/無(wú)
電源電壓: 3.135 V ~ 3.465 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 24-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 24-TSSOP
包裝: 帶卷 (TR)
其它名稱: 843003AGLFT
ICS843003
FEMTOCLOCKS CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
IDT / ICS LVPECL FREQUENCY SYNTHESIZER
6
ICS843003AG REV. A FEBRUARY 19, 2008
Table 4C. LVPECL DC Characteristics, VCC = VCCA = VCCO_A = VCCO_B = 3.3V ± 5%, VEE = 0V, TA = 0°C to 70°C
NOTE 1: Outputs termination with 50
to V
CCO_A, _B – 2V.
Table 5. Crystal Characteristics
NOTE: Characterized using an 18pF parallel resonant crystal.
AC Electrical Characteristics
Table 6. AC Characteristics, VCC = VCCA = VCCO_A = VCCO_B = 3.3V ± 5%, VEE = 0V, TA = 0°C to 70°C
NOTE 1: Defined as skew within a bank of outputs at the same voltages and with equal load conditions.
NOTE 2: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Please refer to the Phase Noise Plots.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
VOH
Output High Current; NOTE 1
VCCO – 1.4
VCCO – 0.9
A
VOL
Output Low Current; NOTE 1
VCCO – 2.0
VCCO – 1.7
A
VSWING
Peak-to-peak Output Voltage Swing
0.6
1.0
V
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
Mode of Oscillation
Fundamental
Frequency
FB_DIV = ÷20
28
31.25
35
MHz
FB_DIV = ÷24
23.33
26.04166
29.167
MHz
Equivalent Series Resistance (ESR)
50
Shunt Capacitance
7pF
Parameter
Symbol
Test Conditions
Minimum
Typical
Maximum
Units
fOUT
Output Frequency
DIV_SELx[1:0] = 00
560
700
MHz
DIV_SELx[1:0] = 01
280
350
MHz
DIV_SELx[1:0] = 10
140
175
MHz
DIV_SELx[1:0] = 11
112
140
MHz
tsk(b)
Bank Skew, NOTE 1
20
ps
tsk(o)
Output Skew; NOTE 2, 4
Outputs @ Same Frequency
35
ps
Outputs @ Different Frequencies
100
ps
tjit()
RMS Phase Jitter, (Random);
NOTE 3
625MHz, (1.875MHz – 20MHz)
0.42
ps
312.5MHz, (1.875MHz – 20MHz)
0.50
ps
156.25MHz, (1.875MHz – 20MHz)
0.51
ps
125MHz, (1.875MHz – 20MHz)
0.52
ps
tR / tF
Output Rise/Fall Time
20% to 80%
250
600
ps
odc
Output Duty Cycle
DIV_SELx[1:0] = 00
40
60
%
DIV_SELx[1:0]
≠ 00
47
53
%
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