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參數(shù)資料
| 型號(hào)： | ICS843002I-41 |
| 英文描述： | 700MHz, FEMTOCLOCKS-TM VCXO BASED SONET/SDH JITTER ATTENUATOR |
| 中文描述： | 700MHz的，F(xiàn)EMTOCLOCKS，商標(biāo)VCXO的基于SONET / SDH的抖動(dòng)衰減器 |
| 文件頁(yè)數(shù)： | 15/21頁(yè) |
| 文件大小： | 279K |
| 代理商： | ICS843002I-41 |
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843002AKI-41
www.icst.com/products/hiperclocks.html
REV. A JUNE 1, 2005
15
Integrated
Circuit
Systems, Inc.
ICS843002I-41
700MH
Z
, F
EMTO
C
LOCKS
VCXO B
ASED
SONET/SDH J
ITTER
A
TTENUATOR
PRELIMINARY
F
IGURE
5C. H
I
P
ER
C
LOCK
S CLK/
N
CLK I
NPUT
D
RIVEN
BY
3.3V LVPECL D
RIVER
F
IGURE
5B. H
I
P
ER
C
LOCK
S CLK/
N
CLK I
NPUT
D
RIVEN
BY
3.3V LVPECL D
RIVER
F
IGURE
5D. H
I
P
ER
C
LOCK
S CLK/
N
CLK I
NPUT
D
RIVEN
BY
3.3V LVDS D
RIVER
3.3V
R1
50
R3
50
Zo = 50 Ohm
LVPECL
Zo = 50 Ohm
HiPerClockS
Input
CLK
nCLK
3.3V
R2
50
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
3.3V
R3
R2
84
Zo = 50 Ohm
3.3V
R4
LVPECL
R1
84
3.3V
D
IFFERENTIAL
C
LOCK
I
NPUT
I
NTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both V
and V
must meet the
V
and V
input requirements. Figures 5A to 5E show inter-
face examples for the HiPerClockS CLK/nCLK input driven by
the most common driver types. The input interfaces suggested
F
IGURE
5A. H
I
P
ER
C
LOCK
S CLK/
N
CLK I
NPUT
D
RIVEN
BY
ICS H
I
P
ER
C
LOCK
S LVHSTL D
RIVER
here are examples only. Please consult with the vendor of the
driver component to confirm the driver termination requirements.
For example in Figure 5A,the input termination applies for ICS
HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver
from another vendor, use their termination recommendation.
1.8V
R2
50
Input
LVHSTL Driver
ICS
HiPerClockS
R1
50
LVHSTL
3.3V
Zo = 50 Ohm
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
Zo = 50 Ohm
R1
100
3.3V
LVDS_Driver
Zo = 50 Ohm
Receiver
CLK
nCLK
3.3V
F
IGURE
5E. H
I
P
ER
C
LOCK
S CLK/
N
CLK I
NPUT
D
RIVEN
BY
3.3V LVPECL D
RIVER
WITH
AC C
OUPLE
Zo = 50 Ohm
R3
125
HiPerClockS
Input
CLK
nCLK
3.3V
R5
3.3V
R2
84
3.3V
R6
R5,R6 locate near the driver pin.
Zo = 50 Ohm
R1
84
R4
125
C2
LVPECL
C1
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ICS843002 | FEMTOCLOCKS⑩ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER |
| ICS843002AG | FEMTOCLOCKS⑩ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER |
| ICS843002AGLF | FEMTOCLOCKS⑩ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER |
| ICS843002AGLFT | FEMTOCLOCKS⑩ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER |
| ICS843002AGT | FEMTOCLOCKS⑩ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS843002I-72 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:FEMTOCLOCKS⑩ VCXO BASED WCDMA CLOCK GENERATOR/JITTER ATTENUATOR |
| ICS843003 | 制造商:ICS 制造商全稱:ICS 功能描述:FEMTOCLOCKS CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER |
| ICS843003AG | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:FEMTOCLOCKS CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER |
| ICS843003AGI-01 | 制造商:ICS 制造商全稱:ICS 功能描述:FEMTOCLOCKS-TM CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER |
| ICS843003AGI-01LF | 功能描述:IC SYNTHESIZER LVPECL 24-TSSOP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:HiPerClockS™, FemtoClock™ 標(biāo)準(zhǔn)包裝:27 系列:Precision Edge® 類型:頻率合成器 PLL:是 輸入:PECL，晶體 輸出:PECL 電路數(shù):1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無(wú)/是 頻率 - 最大:800MHz 除法器/乘法器:是/無(wú) 電源電壓:3.135 V ~ 5.25 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:28-SOIC 包裝:管件 |
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