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| 型號(hào)： | ICS8421002AGI-01LFT |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁(yè)數(shù)： | 10/14頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC FREQ SYNTHESIZER 20-TSSOP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 系列： | HiPerClockS™, FemtoClock™ |
| 類型： | 頻率合成器 |
| PLL： | 帶旁路 |
| 輸入： | LVCMOS，LVTTL，晶體 |
| 輸出： | LVHSTL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:2 |
| 差分 - 輸入:輸出： | 無(wú)/是 |
| 頻率 - 最大： | 170MHz |
| 除法器/乘法器： | 是/無(wú) |
| 電源電壓： | 2.375 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-TSSOP |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 8421002AGI-01LFT |
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Micrel, Inc.
SY88149NDL
February 2012
5
M9999-020712-A
hbwhelp@micrel.com or (408) 955-1690
AC Electrical Characteristics
VCC = 3.0V to 3.6V; RLOAD = 50 to VCC – 2V; TA = –40°C to +85°C.
Symbol
Parameter
Condition
Min.
Typ.
Max.
Units
tr, tf
Output Rise/Fall Time (20% to 80%)
Note 5
260
ps
tJAM
JAM Enable/Disable Time
2
ns
tAUTORESET
SD Deassert or LOS Assert with Auto Reset
Enabled.
100
120
150
ns
tRESET
RESET Disable Time
Note 6
5
ns
tON
SD Assert Time/LOS Deassert time
5
ns
tJITTER
Deterministic
Random
Note 7
Note 8
15
5
psPP
psRMS
VID
Differential Input Voltage Swing
Figure 1
5
1800
mVPP
VOD
Differential Output Voltage Swing
VID ≥18mVPP
1500
mVPP
SDAL /LOSDL
Low SD Assert/LOS De- Assert Level
RLOS/SDLVL = 10k, Notes
(9, 10)
4
mVPP
SDDL//LOSAL
Low SD Deassert /LOS Assert Level
RLOS/SDLVL = 10k, Notes
(10, 12)
3
mVPP
HYSL
Low SD/LOS Hysteresis
RLOS/SDLVL = 10k, Notes
(11, 12)
5
dB
SDAM/LOSDM
Medium SD Assert/LOS Deassert Level
RLOS/SDLVL = 5k, Notes
(10, 12)
9.5
12.5
16
mVPP
SDDM/LOSAM
Medium SD Deassert /LOS Assert Level
RLOS/SDLVL = 5k, Notes
(10,12)
5
7
8.5
mVPP
HYSM
Medium SD/LOS Hysteresis
RLOS/SDLVL = 5k, Notes
(11, 12)
3.0
4.5
6.5
dB
SDAH/LOSDH
High SD Assert/LOS De- Assert Level
RLOS/SDLVL = 50, Notes
(10, 12)
27
35
45
mVPP
SDDH/LOSAH
High SD Deassert/ LOS Assert Level
RLOS/SDLVL = 50, Notes
(10, 12)
15
21
28
mVPP
HYSH
High SD/LOS Hysteresis
RLOS/SDLVL = 50, Notes
(11, 12)
2.0
3
6
dB
B-3dB
3dB Bandwidth
750
MHz
AV(Diff)
Differential Voltage Gain
48
dB
S21
Single-Ended Small-Signal Gain
42
dB
Notes:
1.
Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied
at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
2.
The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
3.
Thermal performance assumes the use of a 4-layer PCB. Exposed pad must be soldered to the device’s most negative potential on the PCB.
4.
VIHCMR is defined as common mode range of the VIH level on DIN and /DIN. It is the most positive level of the differential input signal when driven
differentially or is the reference level on Din\ when being driven single ended.
5.
Amplifier in limiting mode. Input is a 200MHz square wave.
6.
The time between applying RESET and outputs being disabled.
7.
Deterministic jitter measured using 1.25Gbps K28.7 pattern, VID = 10mVPP.
8.
Random jitter measured using 1.25Gbps K28.7 pattern, VID = 10mVPP.
9.
SD is the opposite polarity of LOS. Therefore, an SD Assert parameter is equivalent to a LOS deassert parameter and vice versa.
10. See “Typical Operating Characteristics” for a graph showing how to choose a particular RLOS/SDLVL for a particular assert and
its associated deassert amplitude.
11. This specification defines electrical hysteresis as 20log(SD assert/SD deassert). The ratio between optical hysteresis and electrical hysteresis is
found to vary between 1.5 and 2 depending upon the level of received optical power and ROSA characteristics. Based upon that ratio, the optical
hysteresis corresponding to the electrical hysteresis range 3dB
6dB, shown in the AC Characteristics table, will be 1.5dB-4dB optical hysteresis.
12. All SD Assert (LOS De-Assert) level, SD De-assert (LOS Assert) level and Hysteresis specifications listed above are specified using a 1010
PON Preamble data pattern at the specified data rate of 1.288 Gbps.
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| ICS8421002AGI-01T | 制造商:ICS 制造商全稱:ICS 功能描述:FEMTOCLOCKS⑩ CRYSTAL-TO-HSTL FREQUENCY SYNTHESIZER |
| ICS8421002AGILF | 功能描述:IC FREQ SYNTHESIZER 20-TSSOP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:HiPerClockS™, FemtoClock™ 標(biāo)準(zhǔn)包裝:27 系列:Precision Edge® 類型:頻率合成器 PLL:是 輸入:PECL，晶體 輸出:PECL 電路數(shù):1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無(wú)/是 頻率 - 最大:800MHz 除法器/乘法器:是/無(wú) 電源電壓:3.135 V ~ 5.25 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:28-SOIC 包裝:管件 |
| ICS8421002AGILFT | 功能描述:IC FREQ SYNTHESIZER 20-TSSOP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:HiPerClockS™, FemtoClock™ 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:時(shí)鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
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| ICS8421002AI | 制造商:ICS 制造商全稱:ICS 功能描述:FEMTOCLOCKS⑩ CRYSTAL-TO-HSTL FREQUENCY SYNTHESIZER |
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