參數(shù)資料
型號(hào): ICS840004BGILF
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 7/19頁
文件大?。?/td> 0K
描述: IC FREQ SYNTHESIZER 20TSSOP
標(biāo)準(zhǔn)包裝: 74
系列: HiPerClockS™, FemtoClock™
類型: 頻率合成器
PLL: 帶旁路
輸入: LVCMOS,LVTTL,晶體
輸出: LVCMOS,LVTTL
電路數(shù): 1
比率 - 輸入:輸出: 2:4
差分 - 輸入:輸出: 無/無
頻率 - 最大: 159.375MHz
除法器/乘法器: 是/無
電源電壓: 2.375 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 20-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 20-TSSOP
包裝: 管件
ICS840004BGI REVISION B JULY 6, 2009
15
2009 Integrated Device Technology, Inc.
ICS840004I Data Sheet
FEMTOCLOCK CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
Schematic Example
Figure 4 shows a schematic example of the ICS840004I. An example
of LVCMOS termination is shown in this schematic. Additional
LVCMOS termination approaches are shown in the LVCMOS
Termination Application Note. In this example, an 18pF parallel
resonant 26.5625MHz crystal is used. The C1= 22pF and C2 = 22pF
are recommended for frequency accuracy. For different board
layouts, the C1 and C2 may be slightly adjusted for optimizing
frequency accuracy. The 1k
pullup or pulldown resistors can be
used for the logic control input pins.
Figure 4. P.C. ICS840004I Schematic Example
VDDA
C2
22pF
VDD
VDDO=3.3V
Unused outputs can be left floating. There should be
no trace attached to unused outputs. Device
characterized and specification limits set with all
outputs terminated.
To Logic
Input
pins
C5
0.1u
C3
10uF
VDD
RU1
1K
VDD
R3
36
To Logic
Input
pins
RD1
Not Install
Zo = 50 Ohm
Set Logic
Input to
'1'
RU2
Not Install
U1
840004i
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
20
19
18
17
F_SEL0
nc
nXTAL_SEL
REF_CLK
OE
MR
nPLL_SEL
VDDA
nc
VDD
XTAL_OUT
XTAL_IN
GND
Q3
Q2
VDDO
F_SEL1
GND
Q0
Q1
X1
VDD
Zo = 50 Ohm
R5
100
XTAL_IN
VDD
LVCMOS
C4
0.01u
VDDO
Set Logic
Input to
'0'
C1
22pF
If not using the crystal input, it can be left
floating. For additional protection the XTAL_IN
pin can be tied to ground.
R4
100
R2
10
Logic Control Input Examples
RD2
1K
C6
0.1u
VDD
XTAL_OUT
Optional Termination
LVCMOS
VDD=3.3V
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