參數(shù)資料
型號: ICS83940DYLFT
英文描述: LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER
中文描述: 低偏移,1到18的LVPECL到的LVCMOS / LVTTL扇出緩沖器
文件頁數(shù): 11/15頁
文件大小: 297K
代理商: ICS83940DYLFT
83940DY
www.icst.com/products/hiperclocks.html
REV. B JUNE 15, 2004
11
Integrated
Circuit
Systems, Inc.
ICS83940D
L
OW
S
KEW
, 1-
TO
-18
LVPECL-
TO
-LVCMOS / LVTTL F
ANOUT
B
UFFER
LVPECL C
LOCK
I
NPUT
I
NTERFACE
The PCLK /nPCLK accepts LVPECL, CML, SSTL and other
differential signals. Both V
and V
must meet the V
and V
input requirements. Figures 2A to 2F show interface
examples for the HiPerClockS PCLK/nPCLK input driven by
the most common driver types. The input interfaces suggested
here are examples only. If the driver is from another vendor,
use their termination recommendation. Please consult with
the vendor of the driver component to confirm the driver ter-
mination requirements.
F
IGURE
2A.
H
I
P
ER
C
LOCK
S PCLK/nPCLK I
NPUT
D
RIVEN
BY
AN
O
PEN
C
OLLECTOR
CML D
RIVER
F
IGURE
2B.
H
I
P
ER
C
LOCK
S PCLK/nPCLK I
NPUT
D
RIVEN
BY
A
B
UILT
-I
N
P
ULLUP
CML D
RIVER
F
IGURE
2C.
H
I
P
ER
C
LOCK
S PCLK/nPCLK I
NPUT
D
RIVEN
BY
A
3.3V LVPECL D
RIVER
F
IGURE
2F.
H
I
P
ER
C
LOCK
S PCLK/nPCLK I
NPUT
D
RIVEN
BY
A
3.3V LVDS D
RIVER
PCLK/nPCLK
2.5V
Zo = 60 Ohm
SSTL
HiPerClockS
PCLK
nPCLK
R2
120
3.3V
R3
120
Zo = 60 Ohm
R1
120
R4
120
2.5V
F
IGURE
2E.
H
I
P
ER
C
LOCK
S PCLK/nPCLK I
NPUT
D
RIVEN
BY
AN
SSTL D
RIVER
PCLK/nPCLK
PCLK
nPCLK
3.3V
R2
50
R1
50
3.3V
Zo = 50 Ohm
CML
3.3V
Zo = 50 Ohm
3.3V
HiPerClockS
Input
PCLK
nPCLK
R2
84
R3
125
Zo = 50 Ohm
R4
125
R1
84
LVPECL
3.3V
3.3V
Zo = 50 Ohm
C2
R2
1K
R5
100
Zo = 50 Ohm
3.3V
3.3V
C1
R3
1K
LVDS
R4
1K
HiPerClockS
PCLK/nPCLK
PCLK
nPCLK
R1
1K
Zo = 50 Ohm
3.3V
3.3V
R5
3.3V
3.3V
HiPerClockS
PCLK/nPCLK
PCLK
nPCLK
R1
R2
R3
84
C1
C2
Zo = 50 Ohm
R4
84
Zo = 50 Ohm
R6
3.3V LVPECL
F
IGURE
2D.
H
I
P
ER
C
LOCK
S PCLK/nPCLK I
NPUT
D
RIVEN
BY
A
3.3V LVPECL D
RIVER
WITH
AC C
OUPLE
3.3V
3.3V
CML Built-In Pullup
R1
100
PCLK
nPCLK
HiPerClockS
PCLK/nPCLK
Zo = 50 Ohm
Zo = 50 Ohm
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