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參數(shù)資料
| 型號(hào)： | ICS83940DYLFT |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 3/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK BUFFER MUX 2:18 32-LQFP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 系列： | HiPerClockS™ |
| 類型： | 扇出緩沖器（分配），多路復(fù)用器 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:18 |
| 差分 - 輸入:輸出： | 是/無 |
| 輸入： | CML，LVCMOS，LVPECL，LVTTL，SSTL |
| 輸出： | LVCMOS，LVTTL |
| 頻率 - 最大： | 250MHz |
| 電源電壓： | 2.375 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-LQFP |
| 供應(yīng)商設(shè)備封裝： | 32-TQFP（7x7） |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 83940DYLFT |
83940DY
www.idt.com
REV. B AUGUST 9, 2010
11
ICS83940D
LOW SKEW, 1-TO-18
LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER
LVPECL CLOCK INPUT INTERFACE
The PCLK /nPCLK accepts LVPECL, CML, SSTL and other
differential signals. Both V
SWING and VOH must meet the VPP
and V
CMR input requirements. Figures 2A to 2F show interface
examples for the PCLK/nPCLK input driven by the most
common driver types. The input interfaces suggested here
are examples only. If the driver is from another vendor, use
their termination recommendation. Please consult with the
vendor of the driver component to confirm the driver
termination requirements.
FIGURE 2A. PCLK/nPCLK INPUT DRIVEN
BY AN
OPEN COLLECTOR CML DRIVER
FIGURE 2B. PCLK/nPCLK INPUT DRIVEN
BY A
BUILT-IN PULLUP CML DRIVER
FIGURE 2C. PCLK/nPCLK INPUT DRIVEN
BY A
3.3V LVPECL DRIVER
FIGURE 2F. PCLK/nPCLK INPUT DRIVEN
BY A
3.3V LVDS DRIVER
PCLK/nPCLK
2.5V
Zo = 60 Ohm
SSTL
HiPerClockS
PCLK
nPCLK
R2
120
3.3V
R3
120
Zo = 60 Ohm
R1
120
R4
120
2.5V
FIGURE 2E. PCLK/nPCLK INPUT DRIVEN
BY AN
SSTL DRIVER
HiPerClockS
PCLK
nPCLK
PCLK/nPCLK
3.3V
R2
50
R1
50
3.3V
Zo = 50 Ohm
CML
3.3V
Zo = 50 Ohm
3.3V
HiPerClockS
PCLK
nPCLK
R2
84
R3
125
Input
Zo = 50 Ohm
R4
125
R1
84
LVPECL
3.3V
Zo = 50 Ohm
C2
R2
1K
R5
100
Zo = 50 Ohm
3.3V
C1
R3
1K
LVDS
R4
1K
HiPerClockS
PCLK
nPCLK
R1
1K
Zo = 50 Ohm
3.3V
PCL K/n PC LK
3.3V
R5
100 - 200
3.3V
HiPerClockS
PCLK
nPCLK
R1
125
PCLK/nPCLK
R2
125
R3
84
C1
C2
Zo = 50 Ohm
R4
84
Zo = 50 Ohm
R6
100 - 200
3.3V LVPECL
FIGURE 2D. PCLK/nPCLK INPUT DRIVEN
BY A
3.3V LVPECL DRIVER WITH AC COUPLE
3.3V
CML Built-In Pullup
R1
100
PCLK
nPCLK
HiPerClockS
PCLK/nPCLK
Zo = 50 Ohm
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| ICS83940DYT | 制造商:ICS 制造商全稱:ICS 功能描述:LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER |
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| ICS83947AYI | 制造商:ICS 制造商全稱:ICS 功能描述:LOW SKEW, 1-TO-9 LVCMOS FANOUT BUFFER |
| ICS83947AYI-147 | 制造商:ICS 制造商全稱:ICS 功能描述:LOW SKEW, 1-TO-9 LVCMOS/LVTTL FANOUT BUFFER |
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