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參數(shù)資料
| 型號： | ICS83904AG-02LFT |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 200 MHz, OTHER CLOCK GENERATOR, PDSO16 |
| 封裝： | 4.40 MM X 5 MM, 0.92 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-16 |
| 文件頁數(shù)： | 3/15頁 |
| 文件大?。?/td> | 406K |
| 代理商： | ICS83904AG-02LFT |
IDT / ICS LVCMOS/LVTTL FANOUT BUFFER
11
ICS83904AG-02 REV. A SEPTEMBER 12, 2007
ICS83904-02
LOW SKEW, 1-TO-4, CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER
FIGURE 1. Crystal Input Interface
CRYSTAL INPUT INTERFACE
Figure 1 shows an example of ICS83904-02 crystal interface with
a parallel resonant crystal. The frequency accuracy can be fine
tuned by adjusting the C1 and C2 values. For a parallel crystal
with loading capacitance CL = 18pF, we suggest C1 = 15pF and
C2 = 15pF to start with. These values may be slightly fine tuned
further to optimize the frequency accuracy for different board
layouts. Slightly increasing the C1 and C2 values will slightly reduce
the frequency. Slightly decreasing the C1 and C2 values will slightly
increase the frequency. For the oscillator circuit below, R1 can be
used, but is not required. For new designs, it is recommended
that R1 not be used.
APPLICATION INFORMATION
LVCMOS TO XTAL INTERFACE
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC coupling capacitor. A general interface diagram is
shown in Figure 2. The XTAL_OUT pin can be left floating. The
input edge rate can be as slow as 10ns. For LVCMOS inputs, it is
recommended that the amplitude be reduced from full swing to
half swing in order to prevent signal interference with the power
rail and to reduce noise. This configuration requires that the output
FIGURE 2. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE
impedance of the driver (Ro) plus the series resistance (Rs) equals
the transmission line impedance. In addition, matched termination
at the crystal input will attenuate the signal in half. This can be
done in one of two ways. First, R1 and R2 in parallel should equal
the transmission line impedance. For most 50
Ω applications, R1
and R2 can be 100
Ω. This can also be accomplished by removing
R1 and making R2 50
Ω.
R2
Zo = 50
VDD
Ro
Zo = Ro + Rs
R1
VDD
XTAL_IN
XTAL_OUT
.1uf
Rs
C1
15p
R1 (optional)
0
X1
18pF Parallel Cry stal
C2
15p
XTAL_IN
XTAL_OUT
相關(guān)PDF資料 |
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| ICS83905AMLF | 100 MHz, OTHER CLOCK GENERATOR, PDSO16 |
| ICS83908AGI-02LFT | 200 MHz, OTHER CLOCK GENERATOR, PDSO24 |
| ICS83940AY-01LFT | LOW SKEW CLOCK DRIVER, 18 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| ICS83940AY-01T | LOW SKEW CLOCK DRIVER, 18 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| ICS83940AY-01LF | LOW SKEW CLOCK DRIVER, 18 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS83904AG-02T | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:LOW SKEW, 1-TO-4, CRYSTAL-TOLVCMOS/LVTTL FANOUT BUFFER |
| ICS83904AGI-02LF | 功能描述:IC CLOCK BUFFER MUX 3:4 16-TSSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘緩沖器，驅(qū)動器 系列:HiPerClockS™ 標準包裝:74 系列:- 類型:扇出緩沖器（分配） 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 輸入:HCSL, LVCMOS, LVDS, LVPECL, LVTTL 輸出:HCSL，LVDS 頻率 - 最大:400MHz 電源電壓:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:32-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:32-QFN（5x5） 包裝:管件 |
| ICS83904AGI-02LFT | 功能描述:IC CLOCK BUFFER MUX 3:4 16-TSSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘緩沖器，驅(qū)動器 系列:HiPerClockS™ 標準包裝:74 系列:- 類型:扇出緩沖器（分配） 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 輸入:HCSL, LVCMOS, LVDS, LVPECL, LVTTL 輸出:HCSL，LVDS 頻率 - 最大:400MHz 電源電壓:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:32-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:32-QFN（5x5） 包裝:管件 |
| ICS83905 | 制造商:ICS 制造商全稱:ICS 功能描述:LOW SKEW, 1:6 CRYSTAL INTERFACE-TOLVCMOS / LVTTL FANOUT BUFFER |
| ICS83905_07 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:LOW SKEW, 1:6 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER |
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