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  • 參數(shù)資料
    型號: ICS83840BH
    廠商: INTEGRATED DEVICE TECHNOLOGY INC
    元件分類: 編、解碼器及復(fù)用、解復(fù)用
    英文描述: 83840 SERIES, 10 1 LINE TO 4 LINE MULTIPLEXER, TRUE OUTPUT, PBGA64
    封裝: 7 X 7 MM, 1.20 MM PITCH, TFBGA-64
    文件頁數(shù): 4/8頁
    文件大?。?/td> 270K
    代理商: ICS83840BH
    83840BH
    www.icst.com/products/hiperclocks.html
    REV. A JANUARY 30, 2004
    4
    Integrated
    Circuit
    Systems, Inc.
    ICS83840B
    DDR SDRAM MUX
    t
    PD
    V
    DD
    2
    V
    DD
    2
    PARAMETER MEASUREMENT INFORMATION
    OUTPUT SKEW
    2.5V OUTPUT LOAD AC TEST CIRCUIT
    V
    DD = 1.25V ± 0.1V
    -1.25V ± 0.1V
    PROPAGATION DELAY
    tsk(o)
    V
    DD
    2
    V
    DD
    2
    nDPx
    nDPy
    D or H
    H or D
    tsk(o)
    V
    DD
    2
    V
    DD
    2
    1.25V
    VOH - 0.15V
    VOL
    VOH
    0V
    2.5V
    tPHZ →
    tPZH →
    Output nDPx
    (See Note)
    Sn
    (Low-level
    enabling)
    NOTE: The output is high except when disabled by the Sn control.
    3-STATE OUTPUT ENABLE/DISABLE TIMES
    BANK SKEW (where X denotes outputs in the same bank)
    XDP0:XDP9
    SCOPE
    Qx
    LVCMOS
    V
    DD
    GND
    This circuit is used for test purposes only,
    not intended for application use.
    ICS83840B
    DDR SDRAM MUX
    TSD
    IDT / ICS DDR SDRAM MUX
    ICS83840B
    4
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