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參數(shù)資料
| 型號： | ICS83115BRLF |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 2/6頁 |
| 文件大小： | 0K |
| 描述： | IC CLK BUFF 1:16 200MHZ 28-SSOP |
| 標(biāo)準(zhǔn)包裝： | 48 |
| 系列： | HiPerClockS™ |
| 類型： | 扇出緩沖器（分配） |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:16 |
| 差分 - 輸入:輸出： | 無/無 |
| 輸入： | LVCMOS，LVTTL |
| 輸出： | LVCMOS，LVTTL |
| 頻率 - 最大： | 200MHz |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SSOP（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-QSOP |
| 包裝： | 管件 |
| 其它名稱： | 800-2385-5 83115BRLF ICS83115BRLF-ND |
IDT / ICS DIFFERENTIAL-TO-LVCMOS ZERO DELAY BUFFER
10
ICS87951I-147 REV A JUNE 21, 2006
ICS87951I-147
LOW SKEW, 1-TO-9, DIFFERENTIAL-TO-LVCMOS ZERO DELAY BUFFER
FIGURE 3C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 3B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 3D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVDS DRIVER
3.3V
R1
50
R3
50
Zo = 50 Ohm
LVPECL
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
3.3V
Input
R2
50
Zo = 50 Ohm
Input
HiPerClockS
CLK
nCLK
3.3V
R3
125
R2
84
Zo = 50 Ohm
3.3V
R4
125
LVPECL
R1
84
3.3V
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both V
SWING and VOH must meet the
V
PP and VCMR input requirements.
Figures 3A to 3D show interface
examples for the HiPerClockS CLK/nCLK input driven by the most
common driver types. The input interfaces suggested here are
FIGURE 3A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
ICS HIPERCLOCKS LVHSTL DRIVER
examples only. Please consult with the vendor of the driver
component to confirm the driver termination requirements. For
example in
Figure 3A, the input termination applies for ICS
HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver
from another vendor, use their termination recommendation.
1.8V
R2
50
Input
LVHSTL Driver
ICS
HiPerClockS
R1
50
LVHSTL
3.3V
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
Zo = 50 Ohm
R1
100
3.3V
LVDS_Driv er
Zo = 50 Ohm
Receiv er
CLK
nCLK
3.3V
INPUTS:
CLK INPUT:
For applications not requiring the use of a clock input, it can be
left floating. Though not required, but for additional protection, a
1k
resistor can be tied from the CLK input to ground.
CLK/nCLK INPUT:
For applications not requiring the use of the differential input,
both CLK and nCLK can be left floating. Though not required, but
for additional protection, a 1k
resistor can be tied from CLK to
ground.
LVCMOS CONTROL PINS:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1k
resistor can be used.
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
OUTPUTS:
LVCMOS OUTPUT:
All unused LVCMOS output can be left floating. There should be
no trace attached.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS83115BRLFT | 功能描述:IC CLK BUFF 1:16 200MHZ 28-SSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘緩沖器，驅(qū)動器 系列:HiPerClockS™ 標(biāo)準(zhǔn)包裝:74 系列:- 類型:扇出緩沖器（分配） 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 輸入:HCSL, LVCMOS, LVDS, LVPECL, LVTTL 輸出:HCSL，LVDS 頻率 - 最大:400MHz 電源電壓:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:32-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:32-QFN（5x5） 包裝:管件 |
| ICS83115BRT | 制造商:ICS 制造商全稱:ICS 功能描述:LOW SKEW, 1-TO-16 LVCMOS / LVTTL FANOUT BUFFER |
| ICS8312 | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:LOW SKEW, 1-TO-12 LVCMOS / LVTTL FANOUT BUFFER |
| ICS8312AY | 制造商:Integrated Device Technology Inc 功能描述: |
| ICS8312AYI | 制造商:ICS 制造商全稱:ICS 功能描述:LOW SKEW, 1-TO-12 LVCMOS / LVTTL FANOUT BUFFER |
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