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| 型號： | ICS8305AG-02T |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 8305 SERIES, LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| 封裝： | 4.40 MM X 5.0 MM, 0.92 MM HEIGHT, MO-153, TSSOP-16 |
| 文件頁數(shù)： | 15/16頁 |
| 文件大小： | 1921K |
| 代理商： | ICS8305AG-02T |
IDT / ICS LVCMOS FANOUT BUFFER
8
ICS8305AG-02 REV. A NOVEMBER 13, 2006
ICS8305-02
LOW SKEW, 1-TO-4 MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS FANOUT BUFFER
PRELIMINARY
ADDITIVE PHASE JITTER
Additive Phase Jitter
@ 155.52MHz (12kHz to 20MHz)
= 0.18ps typical
The spectral purity in a band at a specific offset from the
fundamental compared to the power of the fundamental is called
the
dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise power
present in a 1Hz band at a specified offset from the fundamental
frequency to the power value of the fundamental. This ratio is
expressed in decibels (dBm) or a ratio of the power in the 1Hz
As with most timing specifications, phase noise measurements
have issues. The primary issue relates to the limitations of the
equipment. Often the noise floor of the equipment is higher than
the noise floor of the device. This is illustrated above. The device
band to the power in the fundamental. When the required offset
is specified, the phase noise is called a
dBc value, which simply
means dBm at a specified offset from the fundamental. By
investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the
entire time record of the signal. It is mathematically possible to
calculate an expected bit error rate given a phase noise plot.
meets the noise floor of what is shown, but can actually be lower.
The phase noise is dependant on the input source and
measurement equipment.
OFFSET FROM CARRIER FREQUENCY (HZ)
SSB
P
HASE
N
OISE
dB
c
/H
Z
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| ICS8305AGILFT | 8305 SERIES, LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| ICS8305AGIT | 8305 SERIES, LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| ICS8305AG | 8305 SERIES, LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS8305AGI | 制造商:ICS 制造商全稱:ICS 功能描述:LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER |
| ICS8305AGILF | 功能描述:IC CLOCK BUFFER MUX 2:4 16-TSSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘緩沖器，驅(qū)動器 系列:HiPerClockS™ 產(chǎn)品培訓(xùn)模塊:High Bandwidth Product Overview 標(biāo)準(zhǔn)包裝:1,000 系列:Precision Edge® 類型:扇出緩沖器（分配） 電路數(shù):1 比率 - 輸入:輸出:1:4 差分 - 輸入:輸出:是/是 輸入:CML，LVDS，LVPECL 輸出:CML 頻率 - 最大:2.5GHz 電源電壓:2.375 V ~ 2.625 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應(yīng)商設(shè)備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) |
| ICS8305AGILFT | 功能描述:IC CLOCK BUFFER MUX 2:4 16-TSSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘緩沖器，驅(qū)動器 系列:HiPerClockS™ 標(biāo)準(zhǔn)包裝:74 系列:- 類型:扇出緩沖器（分配） 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 輸入:HCSL, LVCMOS, LVDS, LVPECL, LVTTL 輸出:HCSL，LVDS 頻率 - 最大:400MHz 電源電壓:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:32-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:32-QFN（5x5） 包裝:管件 |
| ICS8305AGIT | 制造商:ICS 制造商全稱:ICS 功能描述:LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER |
| ICS8305AGLF | 功能描述:IC CLOCK BUFFER MUX 2:4 16-TSSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘緩沖器，驅(qū)動器 系列:HiPerClockS™ 產(chǎn)品培訓(xùn)模塊:High Bandwidth Product Overview 標(biāo)準(zhǔn)包裝:1,000 系列:Precision Edge® 類型:扇出緩沖器（分配） 電路數(shù):1 比率 - 輸入:輸出:1:4 差分 - 輸入:輸出:是/是 輸入:CML，LVDS，LVPECL 輸出:CML 頻率 - 最大:2.5GHz 電源電壓:2.375 V ~ 2.625 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應(yīng)商設(shè)備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) |
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