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| 型號(hào)： | ICS83054AGI-01LFT |
| 元件分類： | 編、解碼器及復(fù)用、解復(fù)用 |
| 英文描述： | 83054 SERIES, QUAD 2 LINE TO 1 LINE MULTIPLEXER, TRUE OUTPUT, PDSO16 |
| 封裝： | 4.40 X 3 MM, 0.92MM HEIGHT, MO-153, TSSOP-16 |
| 文件頁(yè)數(shù)： | 10/12頁(yè) |
| 文件大?。?/td> | 223K |
| 代理商： | ICS83054AGI-01LFT |
Integrated
Circuit
Systems, Inc.
83054AGI-01
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 24, 2004
7
ICS83054I-01
4-BIT, 2:1,
SINGLE-ENDED MULTIPLEXER
PRELIMINARY
ADDITIVE PHASE JITTER
Additive Phase Jitter (Random)
at 155.52MHz (12KHz - 20MHz)
= 0.07ps (typical)
0
-10
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The spectral purity in a band at a specific offset from the funda-
mental compared to the power of the fundamental is called the
dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise
power present in a 1Hz band at a specified offset from the fun-
damental frequency to the power value of the fundamental. This
ratio is expressed in decibels (dBm) or a ratio of the power in
As with most timing specifications, phase noise measure-
ments have issues. The primary issue relates to the limita-
tions of the equipment. Often the noise floor of the equipment
is higher than the noise floor of the device. This is illustrated
the 1Hz band to the power in the fundamental. When the re-
quired offset is specified, the phase noise is called a
dBc value,
which simply means dBm at a specified offset from the funda-
mental. By investigating jitter in the frequency domain, we get a
better understanding of its effects on the desired application over
the entire time record of the signal. It is mathematically possible
to calculate an expected bit error rate given a phase noise plot.
above. The device meets the noise floor of what is shown, but
can actually be lower. The phase noise is dependant on the
input source and measurement equipment.
OFFSET FROM CARRIER FREQUENCY (HZ)
SSB
P
HASE
N
OISE
dBc/H
Z
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| ICS83056AGI-01LF | 83056 SERIES, HEX 2 LINE TO 1 LINE MULTIPLEXER, TRUE OUTPUT, PDSO20 |
| ICS83056AGI | 83056 SERIES, 6 LINE TO 1 LINE MULTIPLEXER, TRUE OUTPUT, PDSO16 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS83054AGILF | 功能描述:IC CLOCK MUX 2:1 250MHZ 16-TSSOP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘緩沖器，驅(qū)動(dòng)器 系列:HiPerClockS™ 產(chǎn)品培訓(xùn)模塊:High Bandwidth Product Overview 標(biāo)準(zhǔn)包裝:1,000 系列:Precision Edge® 類型:扇出緩沖器（分配） 電路數(shù):1 比率 - 輸入:輸出:1:4 差分 - 輸入:輸出:是/是 輸入:CML，LVDS，LVPECL 輸出:CML 頻率 - 最大:2.5GHz 電源電壓:2.375 V ~ 2.625 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應(yīng)商設(shè)備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) |
| ICS83054AGILFT | 功能描述:IC CLOCK MUX 2:1 250MHZ 16-TSSOP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘緩沖器，驅(qū)動(dòng)器 系列:HiPerClockS™ 標(biāo)準(zhǔn)包裝:74 系列:- 類型:扇出緩沖器（分配） 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 輸入:HCSL, LVCMOS, LVDS, LVPECL, LVTTL 輸出:HCSL，LVDS 頻率 - 最大:400MHz 電源電壓:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:32-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:32-QFN（5x5） 包裝:管件 |
| ICS83054AGIT | 制造商:ICS 制造商全稱:ICS 功能描述:4 : 1, SINGLE-ENDED MULTIPLEXER |
| ICS83054I | 制造商:ICS 制造商全稱:ICS 功能描述:4 : 1, SINGLE-ENDED MULTIPLEXER |
| ICS83054I-01 | 制造商:ICS 制造商全稱:ICS 功能描述:4-BIT, 2 : 1, SINGLE-ENDED MULTIPLEXER |
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