參數(shù)資料
型號(hào): ICS83023AMILFT
英文描述: DIFFERENTIAL-TO-LVCMOS TRANSLATOR/BUFFER
中文描述: 差分至的LVCMOS翻譯/緩沖區(qū)
文件頁(yè)數(shù): 7/12頁(yè)
文件大?。?/td> 159K
代理商: ICS83023AMILFT
83023AMI
www.icst.com/products/hiperclocks.html
REV. B JANUARY 18, 2006
7
Integrated
Circuit
Systems, Inc.
ICS83023I
D
UAL
, 1-
TO
-1
D
IFFERENTIAL
-
TO
-LVCMOS T
RANSLATOR
/B
UFFER
A
PPLICATION
I
NFORMATION
Figure 1
shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V
/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The
F
IGURE
1. S
INGLE
E
NDED
S
IGNAL
D
RIVING
D
IFFERENTIAL
I
NPUT
W
IRING
THE
D
IFFERENTIAL
I
NPUT
TO
A
CCEPT
S
INGLE
E
NDED
L
EVELS
ratio of R1 and R2 might need to be adjusted to position the
V_REF in the center of the input voltage swing. For example, if
the input clock swing is only 2.5V and V
DD
= 3.3V, V_REF should
be 1.25V and R2/R1 = 0.609.
V_REF
R1
1K
C1
0.1u
R2
1K
Single Ended Clock Input
CLK
nCLK
VDD
I
NPUTS
:
CLK/nCLK I
NPUT
:
For applications not requiring the use of the differential input,
both CLK and nCLK can be left floating. Though not required,
but for additional protection, a 1k
Ω
resistor can be tied from
CLK to ground.
R
ECOMMENDATIONS
FOR
U
NUSED
I
NPUT
AND
O
UTPUT
P
INS
O
UTPUTS
:
LVCMOS O
UTPUT
:
All unused LVCMOS output can be left floating. We
recommend that there is no trace attached.
相關(guān)PDF資料
PDF描述
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ICS83023AMI DUAL, 1-TO-1 DIFFERENTIAL-TO-LVCMOS TRANSLATOR/BUFFER
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