參數(shù)資料
型號: ICS830154AMI-08LFT
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 4/16頁
文件大?。?/td> 0K
描述: IC CLOCK BUFFER 1:4 160MHZ 8SOIC
標(biāo)準(zhǔn)包裝: 2,500
系列: HiPerClockS™
類型: 扇出緩沖器(分配)
電路數(shù): 1
比率 - 輸入:輸出: 1:4
差分 - 輸入:輸出: 無/無
輸入: LVCMOS
輸出: LVCMOS
頻率 - 最大: 160MHz
電源電壓: 1.4 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 8-SOIC
包裝: 帶卷 (TR)
ICS830154AGI-08 REVISION A MARCH 29, 2010
12
2010 Integrated Device Technology, Inc.
ICS830154I-08 Data Sheet
OVER-VOLTAGE TOLERANT 1.5V, 1:4 FANOUT BUFFER
Power Considerations
This section provides information on power dissipation and junction temperature for the ICS830154I-08.
Equations and example calculations are also provided.
1.
Power Dissipation.
The total power dissipation for theICS830154I-08 is the sum of the core power plus the power dissipation in the load(s). The following is the
power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.
Power (core)MAX = VDD_MAX * IDD_MAX = 3.465V *1mA = 3.465mW
Total Static Power:
= Power (core)MAX = 3.465mW
Dynamic Power Dissipation at FOUT_MAX (160MHz)
Total Power (160MHz) = [(CPD * N) * Frequency * (VDDO)
2] = [(14pF *4) * 160MHz * (3.465V)2] = 107.6mW
N = number of outputs
Total Power
= Static Power + Dynamic Power Dissipation
= 3.465mW + 107.6mW
= 111.065mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad, and directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj =
θ
JA * Pd_total + TA
Tj = Junction Temperature
θ
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
θ
JA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 121.5°C/W per Table 6A below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.111W *121.5°C/W = 98.5°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 6A. Thermal Resistance θJA for 8 Lead TSSOP, Forced Convection
Table 6B. Thermal Resistance θJA for 8 Lead SOIC, Forced Convection
θ
JA by Velocity
Meters per Second
01
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
121.5°C/W
117.3°C/W
115.3°C/W
θ
JA by Velocity
Meters per Second
01
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
103°C/W
94°C/W
89°C/W
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