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參數(shù)資料
| 型號(hào)： | ICS82C404XXCN16 |
| 英文描述： | Peripheral IC |
| 中文描述： | 外圍芯片 |
| 文件頁數(shù)： | 5/13頁 |
| 文件大?。?/td> | 610K |
| 代理商： | ICS82C404XXCN16 |
Serial Programming Architecture
The pins SEL0 and SEL1 perform the dual functions of select-
ing registers and serial programming. In serial programming
mode, SEL0 acts as a clock pin while SEL1 acts as the data pin.
The
ICS82C404-01
may not be serially programmed when in
power-down mode.
In order to program a particular register, an unlocking sequence
must occur. The unlocking sequence is detailed in the following
timing diagram:
The unlock sequence consists of at least five low-to-high
transitions of CLK while data is high, followed immediately
by a single low-to-high transition while data is low. Following
this unlock sequence, data can be loaded into the serial data
register.
Following any transition of CLK or DATA, the watchdog timer
is reset and begins counting. The watchdog timer ensures that
successive rising edges of CLK and DATA do not violate the
time-out specification of 2ms. If a time-out occurs, the lock
mechanism is reset and the data in the serial data register is
ignored.
Figure 1: Serial Data Timing
Since the VCLK registers are selected by the SEL0 and SEL1
pins, and since any change in their state may affect the output
frequency, new data input on the selection bits is only permitted
to pass through the decode logic after the watchdog timer has
timed out. This delay of SEL0 or SEL1 data permits a serial
program cycle to occur without affecting the current register
selection.
Serial Data Register
The serial data is clocked into the serial data register in the
order described in Figure 1 below (Serial Data Timing).
The serial data is sent as follows: An individual data bit is
sampled on the rising edge of CLK. The complement of the
data bit must be sampled on the previous falling edge of CLK.
The set-up and hold time requirements must be met on both
CLK edges. For specifics on timing, see the timing diagrams
on pages 10, 11 and 12.
The bits are shifted in this order: a start bit, 21 data bits, 3
address bits (which designate the desired register), and a stop
bit. A total of 24 bits must always be loaded into the serial data
register or an error is issued. Following the entry of the last
data bit, a stop bit or load command is issued by bringing DATA
high and toggling CLK high-to-low and low-to-high. The
unlocking mechanism then resets itself following the load.
Only after a time-out period are the SEL0 and SEL1 pins
allowed to return to a register selection function.
ICS82C404
5
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ICS82C404XXCW16 | Peripheral IC |
| ICS8302-01 | LOW SKEW, 1-TO-2 LVCMOS / LVTTL FANOUT BUFFER W/ COMPLEMENTARY OUTPUT |
| ICS8302AM-01 | LOW SKEW, 1-TO-2 LVCMOS / LVTTL FANOUT BUFFER W/ COMPLEMENTARY OUTPUT |
| ICS8302AM-01T | LOW SKEW, 1-TO-2 LVCMOS / LVTTL FANOUT BUFFER W/ COMPLEMENTARY OUTPUT |
| ICS83021AMILF | 2.5V, 3.3V DIFFERENTIAL-TO-LVCMOS/LVTTL TRANSLATOR |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS82C404XXCW16 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Peripheral IC |
| ICS830154AGI-08LF | 制造商:Integrated Device Technology Inc 功能描述:IC FANOUT BUFFER 1.5V 1:4 8TSSOP 制造商:Integrated Device Technology Inc 功能描述:IC CLK BUFFER 1:4 160MHZ 8TSSOP |
| ICS830154AGI-08LFT | 制造商:Integrated Device Technology Inc 功能描述:IC FANOUT BUFFER 1.5V 1:4 8TSSOP 制造商:Integrated Device Technology Inc 功能描述:IC CLK BUFFER 1:4 160MHZ 8TSSOP |
| ICS830154AMI-08LF | 功能描述:IC CLOCK BUFFER 1:4 160MHZ 8SOIC RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘緩沖器，驅(qū)動(dòng)器 系列:HiPerClockS™ 標(biāo)準(zhǔn)包裝:74 系列:- 類型:扇出緩沖器（分配） 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 輸入:HCSL, LVCMOS, LVDS, LVPECL, LVTTL 輸出:HCSL，LVDS 頻率 - 最大:400MHz 電源電壓:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:32-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:32-QFN（5x5） 包裝:管件 |
| ICS830154AMI-08LFT | 功能描述:IC CLOCK BUFFER 1:4 160MHZ 8SOIC RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘緩沖器，驅(qū)動(dòng)器 系列:HiPerClockS™ 標(biāo)準(zhǔn)包裝:74 系列:- 類型:扇出緩沖器（分配） 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 輸入:HCSL, LVCMOS, LVDS, LVPECL, LVTTL 輸出:HCSL，LVDS 頻率 - 最大:400MHz 電源電壓:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:32-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:32-QFN（5x5） 包裝:管件 |
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