D
參數(shù)資料
型號: ICS813001AGILFT
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 4/18頁
文件大?。?/td> 0K
描述: IC VCXO DUAL MULTIPLER 24-TSSOP
標(biāo)準(zhǔn)包裝: 2,500
系列: HiPerClockS™, FemtoClock™
類型: 多路復(fù)用器,壓控晶體振蕩器(VCXO)
PLL: 帶旁路
輸入: HCSL,LVCMOS,LVDS,LVHSTL,LVPECL,LVTTL,SSTL
輸出: LVPECL
電路數(shù): 1
比率 - 輸入:輸出: 5:1
差分 - 輸入:輸出: 是/是
頻率 - 最大: 640MHz
除法器/乘法器: 是/是
電源電壓: 2.375 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 24-TSSOP
包裝: 帶卷 (TR)
其它名稱: 813001AGILFT
813001AGI
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 31, 2012
12
Integrated
Circuit
Systems, Inc.
ICS813001I
DUAL VCXO W/3.3V, 2.5V LVPECL
FEMTOCLOCK PLL
TERMINATION FOR 3.3V LVPECL OUTPUT
V
CC - 2V
50
Ω
50
Ω
RTT
Z
o = 50Ω
Z
o = 50Ω
FOUT
FIN
RTT =
Z
o
1
((V
OH + VOL) / (VCC – 2)) – 2
3.3V
125
Ω
125
Ω
84
Ω
84
Ω
Z
o = 50Ω
Z
o = 50Ω
FOUT
FIN
The clock layout topology shown below is a typical ter-
mination for LVPECL outputs. The two different layouts
mentioned are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs
that generate ECL/LVPECL compatible outputs. There-
fore, terminating resistors (DC current path to ground)
or current sources must be used for functionality. These
outputs are designed to drive 50
Ω transmission lines.
FIGURE 5B. LVPECL OUTPUT TERMINATION
FIGURE 5A. LVPECL OUTPUT TERMINATION
Matched impedance techniques should be used to maxi-
mize operating frequency and minimize signal distor-
tion.
Figures 5A and 5B show two different layouts which
are recommended only as guidelines. Other suitable
clock layouts may exist and it would be recommended
that the board designers simulate to guarantee compat-
ibility across all printed circuit and clock component pro-
cess variations.
INPUTS:
CRYSTAL INPUT:
For applications not requiring the use of the crystal oscillator
input, both XTAL_IN and XTAL_OUT can be left floating.
Though not required, but for additional protection, a 1k
Ω
resistor can be tied from XTAL_IN to ground.
CLK INPUT:
For applications not requiring the use of a clock input, it can
be left floating. Though not required, but for additional
protection, a 1k
Ω resistor can be tied from the CLK input to
ground.
CLK/nCLK INPUT:
For applications not requiring the use of the differential input,
both CLK and nCLK can be left floating. Though not required,
but for additional protection, a 1k
Ω resistor can be tied from
CLK to ground.
LVCMOS CONTROL PINS:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1k
Ω resistor can be used.
VC input pin - do not float, must be biased.
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
OUTPUTS:
LVPECL OUTPUT
All unused LVPECL outputs can be left floating. We
recommend that there is no trace attached. Both sides of the
differential output pair should either be left floating or
terminated.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ICS813001AGIT 制造商:ICS 制造商全稱:ICS 功能描述:DUAL VCXO W/3.3V, 2.5V LVPECL FEMTOCLOCK-TM PLL
ICS813001I 制造商:ICS 制造商全稱:ICS 功能描述:DUAL VCXO W/3.3V, 2.5V LVPECL FEMTOCLOCK-TM PLL
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