參數(shù)資料
型號: ICS81006AKILF
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 13/15頁
文件大小: 0K
描述: IC VCXO TO 6 LVCMOS OUT 20VFQFPN
標(biāo)準(zhǔn)包裝: 75
系列: HiPerClockS™
類型: 壓控晶體振蕩器(VCXO)
PLL:
輸入: 晶體
輸出: LVCMOS,LVTTL
電路數(shù): 1
比率 - 輸入:輸出: 1:6
差分 - 輸入:輸出: 無/無
頻率 - 最大: 31.25MHz
除法器/乘法器: 是/無
電源電壓: 1.6 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 20-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 20-VFQFPN(4x4)
包裝: 管件
其它名稱: 81006AKILF
2006 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FMS6146 Rev. 1.1.0
7
FMS6146
Low-Cost
Six-Channel
4th-Order
Standard
De
nition
V
ideo
Filter
Driver
Application Information
Application Circuits
The FMS6146 Low Cost Video Filter (LCVF) provides
6dB gain from input to output. In addition, the input is
slightly offset to optimize the output driver performance.
The offset is held to the minimum required value to
decrease the standing DC current into the load. Typical
voltage levels are shown in the diagram below:
There is a 280mV offset from the DC input level to the
DC output level. VOUT = 2 * VIN + 280mV.
0.0 -> 0.02V
0.3 -> 0.32V
0.65 -> 0.67V
1.0 -> 1.02V
VIN
0.28V
0.88V
1.58V
2.28V
Driven by:
DC-Coupled DAC Outputs
AC-Coupled and Clamped
Y, CV, R, G, B
VOUT
0.15V
0.5V
0.85V
VIN
0.58V
1.28V
1.98V
Driven by:
AC-Coupled and Biased
U, V, Pb, Pr, C
VOUT
Figure 7. Typical Voltage Levels
The FMS6146 provides an internal diode clamp to sup-
port AC-coupled input signals. If the input signal does not
go below ground, the input clamp does not operate. This
allows DAC outputs to directly drive the FMS6146 without
an AC coupling capacitor. When the input is AC coupled,
the diode clamp sets the sync tip (or lowest voltage) just
below ground. The worst-case sync tip compression due
to the clamp cannot exceed 7mV. The input level set by
the clamp, combined with the internal DC offset, keeps
the output within its acceptable range.
For symmetric signals like Chroma, U, V, Pb, and Pr, the
average DC bias is fairly constant and the inputs can be
AC coupled with the addition of a pull-up resistor to set
the DC input voltage. DAC outputs can also drive these
same signals without theAC coupling capacitor. Aconceptual
illustration of the input clamp circuit is shown in Figure 8.
YOUT
Video Cables
75
Ω
75
Ω
75
Ω
75
Ω
Driver
YIN
LOAD1
LOAD2
(optional)
0.65V
Figure 8. Input Clamp Circuit
I/O Congurations
For a DC-coupled DAC drive with DC-coupled outputs,
use the conguration shown in Figure 9.
DVD or
STB
SoC
DAC
Output
75
Ω
LCVF
Clamp
Inactive
0V - 1.4V
Figure 9. DC-Coupled Inputs and Outputs
Alternatively, if the DAC’s average DC output level causes
the signal to exceed the range of 0V to 1.4V, it can be AC
coupled as shown in Figure 10.
DVD or
STB
SoC
DAC
Output
LCVF
Clamp
Active
0.1μ
0V - 1.4V
75Ω
Figure 10. AC-Coupled Inputs,
DC-Coupled Outputs
When the FMS6146 is driven by an unknown external
source or a SCART switch with its own clamping circuitry,
the inputs should be AC coupled as shown in Figure 11.
75Ω
LCVF
Clamp
Active
0.1μ
External video
source must
be AC-coupled
0V - 1.4V
75Ω
Figure 11. SCART with DC-Coupled Outputs
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