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| 型號： | ICS674R-01T |
| 英文描述： | User Configurable Divider |
| 中文描述： | 用戶可配置的分頻器 |
| 文件頁數(shù)： | 5/6頁 |
| 文件大小： | 51K |
| 代理商： | ICS674R-01T |
ICS674-01
User Configurable Divider
MDS 674-01 A
Integrated Circuit Systems 525 Race Street San Jose CA 95126 (408)295-9800tel(408)295-9818fax
5
Revision 033199
Printed 11/15/00
PRELIMINARY INFORMATION
Parameter
ABSOLUTE MAXIMUM RATINGS (stresses be ond these can permanentl damage the device)
Supply Voltage, VDD
Inputs
Clock Output
Ambient Operating Temperature
Ambient Operating Temperature
Soldering Temperature
Storage Temperature
DC CHARACTERISTICS (VDD = 5.0V unless otherwise noted)
Operating Voltage, VDD
Input High Voltage, VIH
Input Low Voltage, VIL
Input High Voltage, VIH, INA and INB only
Input Low Voltage, VIL, INA and INB only
Output High Voltage, VOH
Output Low Voltage, VOL
IDD, Op. Supply Cur., DivA=DivB=20 at 3.3 V
IDD, Op. Supply Cur., DivA=DivB=20 at 5 V
Short Circuit Current, outputs
On-Chip Pull-up Resistor
Input Capacitance
AC CHARACTERISTICS (VDD = 5.0V unless otherwise noted)
Input Frequency, Divider A
Input Frequency, Divider B
Input Frequency, Divider A
Input Frequency, Divider B
Input Frequency, Divider A (Industrial temperature) at 3.3 V at 85 °C
Input Frequency, Divider B (Industrial temperature) at 3.3 V at 85 °C
Input Frequency, Divider A (Industrial temperature) at 5 V at 85 °C
Input Frequency, Divider B (Industrial temperature) at 5 V at 85 °C
Output Clock Rise Time
Output Clock Fall Time
OUTB Clock Duty Cycle (see note)
OUTB Clock Duty Cycle, odd post dividers
OUTA Clock Duty Cycle (see note)
Conditions
Minimum
Typical
Maximum
Units
Referenced to GND
Referenced to GND
Referenced to GND
7
V
V
V
°C
°C
°C
°C
-0.5
-0.5
0
-40
VDD+0.5
VDD+0.5
70
85
260
150
I version
Max of 10 seconds
-65
3
2
5.5
V
V
V
V
V
V
V
All A, B, and S pins
All A, B, and S pins
0.8
(VDD/2)+1
VDD/2
VDD/2
(VDD/2)-1
IOH=-25mA
IOL=25mA
No Load, fin=100 MHz
No Load, fin=100 MHz
2.4
0.4
3
5
mA
mA
mA
k
pF
±70
270
5
A, B, S select pins
A, B, S select pins
at 3.3 V
at 3.3 V
at 5 V
at 5 V
0
0
0
0
0
0
0
0
135
180
200
235
125
170
190
220
55
60
98.5
MH z
MH z
MH z
MH z
MH z
MH z
MH z
MH z
ns
ns
%
%
%
0.8 to 2.0V
2.0 to 0.8V
at VDD/2
at VDD/2, except PD=1
at VDD/2
1
1
45
40
20
49 to 51
Note:
The duty cycle of OUTA is dependent on the selected divide. This is because OUTA goes low for 2 input
clock cycles on INA. So, for example, if a divide of 20 is selected, the duty cycle will be 90%.
Similarly, if PD=1 is selected for OUTB, the duty cycle will be dependent on the selected divide. In this
case OUTB goes high for approximately 8 input clock cycles on INB.
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