- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄360755 > ICS673M-01I PLL Building Block PDF資料下載
參數(shù)資料
| 型號： | ICS673M-01I |
| 英文描述： | PLL Building Block |
| 中文描述： | 鎖相環(huán)積木 |
| 文件頁數(shù)： | 7/9頁 |
| 文件大小： | 73K |
| 代理商： | ICS673M-01I |
ICS673-01
PLL Building Block
MDS 673-01 D
Integrated Circuit Systems, Inc. 525 Race Street San Jose CA 95126(408)295-9800tel www.icst.com
7
Revision 022500
Printed 11/15/00
Avoiding PLL Lockup
In some applications, the ICS673 can “l(fā)ock up” at
the maximum VCO frequency. This is usually
caused by power supply glitches or a very slow
power supply ramp. This situation also occurs if
the external divider starts to fail at high input
frequencies. The usual failure mode of a divider
circuit is that the output of the divider begins to
miss clock edges. The phase detector interprets
this as a too low output frequency and increases
the VCO frequency. The feedback divider begins
to miss even more clock edges, and the VCO
frequency is continually increased until it is
running at the maximum. Whether caused by
power supply issues or by the external divider, the
loop can only recover by powering down the
circuit, asserting PD, or shorting the loop filter to
ground.
The simplest way to avoid this problem is to use
an external divider that always operates correctly
regardless of the VCO speed. Figures 2 and 3
show that the VCO is capable of high speeds. By
using the internal divide-by-four and/or the
CLK2 output, the maximum VCO frequency can
be divided by 2, 4, or 8 and a slower counter can
be used. Using the ICS673 internal dividers in
this manner does reduce the number of
frequencies that can be exactly synthesized by
forcing the total VCO divide to change in
increments of 2, 4, or 8.
If this lockup problem occurs, there are several
solutions, three of which are described below.
1.If the system has a reset or power good signal,
this should be applied to the PD pin, forcing
the ICS673 to stay powered down until the
power supply voltage has stabilized.
2.If no power good signal is available, a simple
power-on reset circuit can be attached to the
PD pin, as shown in Figure 4 below. When the
power supply ramps up, this circuit holds PD
asserted (device powered down) until the
capacitor charges up.
The circuit of Figure 4A is adequate in most
cases, but the discharge rate of capacitor C3
when VDD goes low is limited by R1. As this
discharge rate determines the minimum reset
time, the circuit of Figure 4B may be used when
a faster reset time is desired. The values of R1
and C3 should be selected to ensure that PD
stays below 1.0 V until the power supply is
stable.
3.A comparator circuit may be used to monitor
the loop filter voltage, as shown in Figure 5.
This circuit will dump the charge off the loop
filter by asserting PD if the VCO begins to run
too fast, and the PLL can recover. A good
choice for this comparator is the National
Semiconductor LMC7211BIM5X. It is low
Figure 4. Power-on Reset Circuits.
VDD
R1
C3
ICS673-01
PD
A. Basic Circuit
B. Faster Discharge
VDD
R1
C3
ICS673-01
PD
D1
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ICS673M-01IT | PLL Building Block |
| ICS673M-01T | PLL Building Block |
| ICS673-01 | PLL Building Block |
| ICS680-01 | Networking Clock Synthesizer and Zero Delay Buffer |
| ICS680G-01 | Networking Clock Synthesizer and Zero Delay Buffer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS673M-01ILF | 功能描述:IC PLL BUILDING BLOCK 16SOIC RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:Precision Edge® 類型:時鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應(yīng)商設(shè)備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
| ICS673M-01ILFT | 功能描述:IC PLL BUILDING BLOCK 16-SOIC RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 時鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無 頻率 - 最大:240MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應(yīng)商設(shè)備封裝:32-TQFP（7x7） 包裝:帶卷 (TR) |
| ICS673M-01IT | 功能描述:IC PLL BUILDING BLOCK 16-SOIC RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 產(chǎn)品變化通告:Product Discontinuation 04/May/2011 標(biāo)準(zhǔn)包裝:96 系列:- 類型:時鐘倍頻器，零延遲緩沖器 PLL:帶旁路 輸入:LVTTL 輸出:LVTTL 電路數(shù):1 比率 - 輸入:輸出:1:8 差分 - 輸入:輸出:無/無 頻率 - 最大:133.3MHz 除法器/乘法器:是/無 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:管件 其它名稱:23S08-5HPGG |
| ICS673M-01LF | 功能描述:IC PLL BUILDING BLOCK 16-SOIC RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 頻率合成器 PLL:是 輸入:晶體 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無/無 頻率 - 最大:1GHz 除法器/乘法器:是/無 電源電壓:4.5 V ~ 5.5 V 工作溫度:-20°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-LSSOP（0.175"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-SSOP 包裝:帶卷 (TR) 其它名稱:NJW1504V-TE1-NDNJW1504V-TE1TR |
| ICS673M-01LFT | 功能描述:IC PLL BUILDING BLOCK 16-SOIC RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 時鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無 頻率 - 最大:240MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應(yīng)商設(shè)備封裝:32-TQFP（7x7） 包裝:帶卷 (TR) |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。