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| 型號： | ICS673-01 |
| 英文描述： | PLL Building Block |
| 中文描述： | 鎖相環(huán)積木 |
| 文件頁數(shù)： | 5/9頁 |
| 文件大?。?/td> | 73K |
| 代理商： | ICS673-01 |
ICS673-01
PLL Building Block
MDS 673-01 D
Integrated Circuit Systems, Inc. 525 Race Street San Jose CA 95126(408)295-9800tel www.icst.com
5
Revision 022500
Printed 11/15/00
Determining the Loop Filter Values
The loop filter components consist of C1, C2, and
RZ. Calculating these values is best illustrated by
an example. Using the example in Figure 1, we can
synthesize 40 MHz from a 200 kHz input.
The phase locked loop may be approximately
described by the following equations:
Natural frequency,
ω
n =
Kv Ic
N C
Equation 1
Damping factor,
ζ
=
Rz
Kv Ic C
N
2
1
Equation 2
where
Kv
= VCO gain (MHz/Volt)
Ic
= Charge pump current (μA)
N
= Total feedback divide
C
1 = Loop filter capacitor (Farads)
R
z = Loop filter resistor (Ohms)
The natural frequency,
ω
n, is approximately equal
to the bandwidth (in radians/sec). As a general
rule, the bandwidth should be at least 10 times less
than the reference frequency, i.e.,
ω
n
≈
2
π
BW
≤
REFIN/10.
In this example, BW = REFIN/20, giving a
bandwidth of 10 kHz.
Using the first equation, C1 can be determined
since all other variables are known. In the example
of Figure 1, N = 200, comprising a divide-by-2 on
the chip and the external divide-by-100. Therefore,
Equation 1 becomes
2
π
10,000 =
95 2 4
200
1
.
C
and
C
1 = 289 pF (270 pF nearest std. value).
Choosing a damping factor of 0.7, Equation 2
becomes
0.7 =
Rz
E
2
95 2 4 270 10
.
12
200
and
R
z = 79.8 k
(82 k
nearest std. value).
The capacitor
C
2 is used to damp transients from
the charge pump and should be at least 20 times
smaller than
C
1, i.e.,
C
2
≤
C
1/20.
Therefore,
C
2 = 13.5 pF (13 pF nearest std. value).
To summarize, to generate 40 MHz from 200
kHz with standard values, the loop filter
components are:
C
1 = 270 pF
C
2 = 13 pF
Rz = 82 k
In general, making
C
1 larger may give improved
loop performance, since it both lowers the
bandwidth and increases the damping factor.
However, it also increases the time for the loop to
lock since the charge pump current has to charge a
larger capacitance.
When choosing either CLK1 or CLK2 to drive the
feedback divider, CLK2 should be used whenever
possible. See the following section, “Avoiding
PLL Lockup”, for additional explanations.
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