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參數(shù)資料
| 型號： | ICS663MILF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 663 SERIES, PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
| 封裝： | 0.150 INCH, ROHS COMPLIANT, SOIC-8 |
| 文件頁數(shù)： | 5/8頁 |
| 文件大?。?/td> | 247K |
| 代理商： | ICS663MILF |
PLL BUILDING BLOCK
MDS 663 E
5
Revision 012006
In te gr ated Circuit Systems ● 525 Ra ce Street, San Jose, CA 9512 6 ● tel (4 08) 297-1 201 ● www.icst.com
ICS663
External Components
The ICS663 requires a minimum number of external
components for proper operation. A decoupling
capacitor of 0.01
F should be connected between VDD
and GND as close to the ICS663 as possible. A series
termination resistor of 33
may be used at the clock
output.
Special considerations must be made in choosing loop
components C1 and C2:
1) The loop capacitors should be a low-leakage type to
avoid leakage-induced phase noise. For this reason,
DO NOT use any type of polarized or electrolytic
capacitors.
2) Microphonics (mechanical board vibration) can also
induce output phase noise when the loop bandwidth is
less than 1 kHz. For this reason, ceramic capacitors
should have C0G or NP0 dielectric. Avoid high-K
dielectrics like Z5U and X7R. These and some other
ceramics have piezoelectric properties that convert
mechanical vibration into voltage noise that interferes
with VCXO operation.
For larger loop capacitor values such as 0.1
F or 1F,
PPS film types made by Panasonic, or metal poly types
made by Murata or Cornell Dubilier are recommended.
For questions or changes regarding loop filter
characteristics, please contact your sales area FAE, or
ICS Applications.
Avoiding PLL Lockup
In some applications, the ICS663 can “l(fā)ock up” at the
maximum VCO frequency. The way to avoid this
problem is to use an external divider that always
operates correctly regardless of the CLK output
frequency. The CLK output frequency may be up to 2x
the maximum Output Clock Frequency listed in the AC
Electrical Characteristics above when the device is in
an unlocked condition. Make sure that the external
divider can operate up to this frequency.
Explanation of Operation
The ICS663 is a PLL building block circuit that includes
an integrated VCO with a wide operating range. The
device uses external PLL loop filter components which
through proper configuration allow for low input clock
reference frequencies, such as a 15.7 kHz Hsync input.
The phase/frequency detector compares the falling
edges of the clocks inputted to FBIN and REFIN. It then
generates an error signal to the charge pump, which
produces a charge proportional to this error. The
external loop filter integrates this charge, producing a
voltage that then controls the frequency of the VCO.
This process continues until the edges of FBIN are
aligned with the edges of the REFIN clock, at which
point the output frequency will be locked to the input
frequency.
Figure 1. Example Configuration -- Generating a 20 MHz clock from a 200 kHz reference
RE F IN
+ 3 .3 or 5 V
VDD
S E L
0.01 F
FBIN
200 kH z
100
D igital D iv ider such as
IC S 674-01
GN D
CLK
LF R
20 M H z
LF
C
1
R
Z
C
2
200 kH z
IC S 663
ICS663
PLL BUILDING BLOCK
TSD
IDT / ICS PLL BUILDING BLOCK
ICS663
5
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| ICS663MILFT | 功能描述:IC PLL BUILDING BLOCK 8-SOIC RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:2,000 系列:- 類型:PLL 時鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無 頻率 - 最大:240MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應(yīng)商設(shè)備封裝:32-TQFP（7x7） 包裝:帶卷 (TR) |
| ICS663MIT | 功能描述:IC PLL BUILDING BLOCK 8-SOIC RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 產(chǎn)品變化通告:Product Discontinuation 04/May/2011 標準包裝:96 系列:- 類型:時鐘倍頻器，零延遲緩沖器 PLL:帶旁路 輸入:LVTTL 輸出:LVTTL 電路數(shù):1 比率 - 輸入:輸出:1:8 差分 - 輸入:輸出:無/無 頻率 - 最大:133.3MHz 除法器/乘法器:是/無 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:管件 其它名稱:23S08-5HPGG |
| ICS663MLF | 功能描述:IC PLL BUILDING BLOCK 8-SOIC RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:1,000 系列:Precision Edge® 類型:時鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應(yīng)商設(shè)備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
| ICS663MLFT | 功能描述:IC PLL BUILDING BLOCK 8-SOIC RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:2,000 系列:- 類型:PLL 時鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無 頻率 - 最大:240MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應(yīng)商設(shè)備封裝:32-TQFP（7x7） 包裝:帶卷 (TR) |
| ICS663MT | 功能描述:IC PLL BUILDING BLOCK 8-SOIC RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 產(chǎn)品變化通告:Product Discontinuation 04/May/2011 標準包裝:96 系列:- 類型:時鐘倍頻器，零延遲緩沖器 PLL:帶旁路 輸入:LVTTL 輸出:LVTTL 電路數(shù):1 比率 - 輸入:輸出:1:8 差分 - 輸入:輸出:無/無 頻率 - 最大:133.3MHz 除法器/乘法器:是/無 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:管件 其它名稱:23S08-5HPGG |
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