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參數(shù)資料
| 型號： | ICS662M-03LF |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 662 SERIES, PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
| 封裝： | 0.150 INCH, LEAD FREE, SOIC-8 |
| 文件頁數(shù)： | 3/6頁 |
| 文件大?。?/td> | 128K |
| 代理商： | ICS662M-03LF |
HDTV Audio/Video Clock Source
MDS 662-03 D
3
Revision 033005
Integrated Circuit Systems, Inc.
● 525 Race Street, San Jose, CA 95126 ● tel (408) 295-9800 ● www.icst.com
ICS662-03
Application Information
Series Termination Resistor
Clock output traces should use series termination. To
series terminate a 50
trace (a commonly used trace
impedance), place a 33
resistor in series with the
clock line, as close to the clock output pin as possible.
The nominal impedance of the clock output is 20
.
Decoupling Capacitors
As with any high performance mixed-signal IC, the
ICS662-03 must be isolated from system power supply
noise to perform optimally.
Decoupling capacitors of 0.01F must be connected
between VDD (pin 2) and the PCB ground plane (pin
3).
PCB Layout Recommendations
For optimum device performance and lowest output
phase noise, the following guidelines should be
observed.
1) Each 0.01F decoupling capacitor should be
mounted on the component side of the board as close
to the VDD pin as possible. No vias should be used
between decoupling capacitor and VDD pin. The PCB
trace to VDD pin should be kept as short as possible,
as should the PCB trace to the ground via. Distance of
the ferrite bead and bulk decoupling from the device is
less critical.
2) To minimize EMI and obtain the best signal integrity,
the 33
series termination resistor should be placed
close to the clock output.
3) An optimum layout is one with all components on the
same side of the board, minimizing vias through other
signal layers (the ferrite bead and bulk decoupling
capacitor can be mounted on the back). Other signal
traces should be routed away from the ICS662-03. This
includes signal traces just underneath the device, or on
layers adjacent to the ground plane layer used by the
device.
相關PDF資料 |
PDF描述 |
|---|---|
| ICS663MILF | 663 SERIES, PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
| ICS664G-01LFT | 74.25 MHz, VIDEO CLOCK GENERATOR, PDSO16 |
| ICS664G-01T | 74.25 MHz, VIDEO CLOCK GENERATOR, PDSO16 |
| ICS664G-01 | 74.25 MHz, VIDEO CLOCK GENERATOR, PDSO16 |
| ICS664GI-01LF | 74.25 MHz, VIDEO CLOCK GENERATOR, PDSO16 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ICS662M-03LFT | 功能描述:IC CLK SOURCE HDTV AUD/VID 8SOIC RoHS:是 類別:集成電路 (IC) >> 線性 - 視頻處理 系列:- 產(chǎn)品變化通告:Product Discontinuation 07/Mar/2011 標準包裝:3,000 系列:OMNITUNE™ 類型:調諧器 應用:移動電話，手機，視頻顯示器 安裝類型:表面貼裝 封裝/外殼:65-WFBGA 供應商設備封裝:PG-WFSGA-65 包裝:帶卷 (TR) 其它名稱:SP000365064 |
| ICS662M-03T | 功能描述:IC CLK SOURCE HDTV AUD/VID 8SOIC RoHS:否 類別:集成電路 (IC) >> 線性 - 視頻處理 系列:- 產(chǎn)品變化通告:Product Discontinuation 07/Mar/2011 標準包裝:3,000 系列:OMNITUNE™ 類型:調諧器 應用:移動電話，手機，視頻顯示器 安裝類型:表面貼裝 封裝/外殼:65-WFBGA 供應商設備封裝:PG-WFSGA-65 包裝:帶卷 (TR) 其它名稱:SP000365064 |
| ICS663 | 制造商:ICS 制造商全稱:ICS 功能描述:PLL BUILDING BLOCK |
| ICS663M | 功能描述:IC PLL BUILDING BLOCK 8-SOIC RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 產(chǎn)品變化通告:Product Discontinuation 04/May/2011 標準包裝:96 系列:- 類型:時鐘倍頻器，零延遲緩沖器 PLL:帶旁路 輸入:LVTTL 輸出:LVTTL 電路數(shù):1 比率 - 輸入:輸出:1:8 差分 - 輸入:輸出:無/無 頻率 - 最大:133.3MHz 除法器/乘法器:是/無 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:管件 其它名稱:23S08-5HPGG |
| ICS663MI | 功能描述:IC PLL BUILDING BLOCK 8-SOIC RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 產(chǎn)品變化通告:Product Discontinuation 04/May/2011 標準包裝:96 系列:- 類型:時鐘倍頻器，零延遲緩沖器 PLL:帶旁路 輸入:LVTTL 輸出:LVTTL 電路數(shù):1 比率 - 輸入:輸出:1:8 差分 - 輸入:輸出:無/無 頻率 - 最大:133.3MHz 除法器/乘法器:是/無 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:管件 其它名稱:23S08-5HPGG |
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