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參數(shù)資料
| 型號： | ICS650R-01T |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 80 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO20 |
| 封裝： | 0.150 INCH, SSOP-20 |
| 文件頁數(shù)： | 3/7頁 |
| 文件大?。?/td> | 147K |
| 代理商： | ICS650R-01T |
System Peripheral Clock Source
MDS 650-01 F
3
Revision 082505
Integrated Circuit Systems, Inc.
● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS650-01
External Components
The ICS650-01 requires a minimum number of external
components for proper operation.
Decoupling Capacitor
Decoupling capacitors of 0.01F must be connected
between each VDD and GND (pins 4 and 6, pins 16
and 14), as close to the device as possible. For
optimum device performance, the decoupling capacitor
should be mounted on the component side of the PCB.
Avoid the use of vias in the decoupling circuit.
Series Termination Resistor
When the PCB trace between the clock outputs and the
loads are over 1 inch, series termination should be
used. To series terminate a 50
trace (a commonly
used trace impedance) place a 33
resistor in series
with the clock line, as close to the clock output pin as
possible. The nominal impedance of the clock output is
20
.
Crystal Information
The crystal used should be a fundamental mode (do
not use third overtone), parallel resonant, 300 ppm or
better (to meet Ethernet specs). Crystal capacitors
should be connected from pins X1 to ground and X2 to
ground to optimize the initial accuracy. The value of
these capacitors is given by the following equation:
Crystal caps (pF) = (CL - 12) x 2
In the equation, CL is the crystal load capacitance. So,
for a crystal with a 16 pF load capacitance, two 8 pF
capacitors should be used. If a clock input is used,
drive it into X1 and leave X2 unconnected.
13
14.318M
Output
14.31818 MHz Buffered reference clock output.
14
GND
Power
Connect to ground.
15
ASEL
Input
ACLK select pin. Determines frequency of Audio clock per table above.
16
VDD
Power
Connect to VDD. Must be same value as other VDD. Decouple with pin 14.
17
PCLK3
Output
PCLK output number 3 per table above.
18
PCLK2
Output
PCLK output number 2 per table above.
19
PSEL0
Input
Processor select pin #0. Determines frequencies on PCLKs 1-4 per table
above.
20
PSEL1
Input
Processor select pin #1. Determines frequencies on PCLKs 1-4 per table
above.
Pin
Number
Pin
Name
Pin
Type
Pin Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ICS650R-05T | 74.25 MHz, VIDEO CLOCK GENERATOR, PDSO20 |
| ICS650R-05 | 74.25 MHz, VIDEO CLOCK GENERATOR, PDSO20 |
| ICS650R-05LFT | 74.25 MHz, VIDEO CLOCK GENERATOR, PDSO20 |
| ICS650R-07ILF | 133.33 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| ICS650R-11I | 133.33 MHz, OTHER CLOCK GENERATOR, PDSO20 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS650R-05 | 制造商:ICS 制造商全稱:ICS 功能描述:HDTV Clock Synthesizer |
| ICS650R-05T | 制造商:ICS 制造商全稱:ICS 功能描述:HDTV Clock Synthesizer |
| ICS650R-07 | 功能描述:IC NETWORKING CLK SOURCE 20-SSOP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 產(chǎn)品變化通告:Product Discontinuation 04/May/2011 標準包裝:96 系列:- 類型:時鐘倍頻器，零延遲緩沖器 PLL:帶旁路 輸入:LVTTL 輸出:LVTTL 電路數(shù):1 比率 - 輸入:輸出:1:8 差分 - 輸入:輸出:無/無 頻率 - 最大:133.3MHz 除法器/乘法器:是/無 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設(shè)備封裝:16-TSSOP 包裝:管件 其它名稱:23S08-5HPGG |
| ICS650R-07I | 功能描述:IC NETWORKING CLK SOURCE 20-SSOP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 產(chǎn)品變化通告:Product Discontinuation 04/May/2011 標準包裝:96 系列:- 類型:時鐘倍頻器，零延遲緩沖器 PLL:帶旁路 輸入:LVTTL 輸出:LVTTL 電路數(shù):1 比率 - 輸入:輸出:1:8 差分 - 輸入:輸出:無/無 頻率 - 最大:133.3MHz 除法器/乘法器:是/無 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設(shè)備封裝:16-TSSOP 包裝:管件 其它名稱:23S08-5HPGG |
| ICS650R-07ILF | 功能描述:IC NETWORKING CLK SOURCE 20-SSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:1,000 系列:- 類型:時鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應商設(shè)備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
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