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參數(shù)資料
| 型號(hào)： | ICS650GI-36LF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 125 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO16 |
| 封裝： | 0.173 INCH, ROHS COMPLIANT, TSSOP-16 |
| 文件頁數(shù)： | 3/8頁 |
| 文件大小： | 255K |
| 代理商： | ICS650GI-36LF |
Networking & PCI Clock Source
MDS 650-36 D
3
Revision 030206
In te gr ated C i rcuit Syste m s
● 525 R ace Street, San Jose, CA 9 5126 ● tel (40 8) 29 7-120 1● www.icst.com
ICS650-36
External Components
Decoupling Capacitor
As with any high performance mixed-signal IC, the
ICS650-36 must be isolated from system power supply
noise to perform optimally.
A decoupling capacitor of 0.01F must be connected
between each VDD and the PCB ground plane.
Series Termination Resistor
Clock output traces over one inch should use series
termination. To series terminate a 50
trace (a
commonly used trace impedance), place a 33
resistor
in series with the clock line, as close to the clock output
pin as possible. The nominal impedance of the clock
output is 20
.
Crystal Load Capacitors
The device crystal connections should include pads for
small capacitors from X1 to ground and from X2 to
ground. These capacitors are used to adjust the stray
capacitance of the board to match the nominally
required crystal load capacitance. Because load
capacitance can only be increased in this trimming
process, it is important to keep stray capacitance to a
minimum by using very short PCB traces (and no vias)
between the crystal and device. Crystal capacitors
must be connected from each of the pins X1 and X2 to
ground.
The value (in pF) of these crystal caps should equal
(CL -6 pF)*2. In this equation, CL= crystal load
capacitance in pF. Example: For a crystal with a 16 pF
load capacitance, each crystal capacitor would be 20
pF [(16-6) x 2 = 20].
PCB Layout Recommendations
Observed the following guidelines for optimum device
performance and lowest output phase noise:
1) The 0.01F decoupling capacitors should be
mounted on the component side of the board as close
to the VDD pin as possible. No vias should be used
between the decoupling capacitors and VDD pins. The
PCB trace to VDD pins should be kept as short as
possible, as should the PCB trace to the ground via.
2) The external crystal should be mounted just next to
the device with short traces. The X1 and X2 traces
should not be routed next to each other with minimum
spaces, instead they should be separated and away
from other traces.
3) Place the 33
series termination resistor (if needed)
close to the clock output to minimize EMI.
4) An optimum layout is one with all components on the
same side of the board, minimizing vias through other
signal layers. Other signal traces should be routed
away from the ICS650-36. This includes signal traces
just underneath the device, or on layers adjacent to the
ground plane layer used by the device.
14
REF
Output
Reference 25 MHz clock output. Weak internal pull-down when
tri-state.
15
GND
Power
Connect to ground.
16
VDD
Power
Connect to +3.3 V.
Pin
Number
Pin
Name
Pin
Type
Pin Description
ICS650-36
Networking & PCI Clock Source
TSD
IDT / ICS Networking & PCI Clock Source
ICS650-36
3
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ICS650R-01IT | 80 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO20 |
| ICS650R-01LF | 80 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO20 |
| ICS650R-01T | 80 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO20 |
| ICS650R-05T | 74.25 MHz, VIDEO CLOCK GENERATOR, PDSO20 |
| ICS650R-05 | 74.25 MHz, VIDEO CLOCK GENERATOR, PDSO20 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS650GI-36LFT | 功能描述:IC CLOCK NETWORK/PCI 16-TSSOP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 時(shí)鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無 頻率 - 最大:240MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應(yīng)商設(shè)備封裝:32-TQFP（7x7） 包裝:帶卷 (TR) |
| ICS650GI-36T | 制造商:ICS 制造商全稱:ICS 功能描述:Networking & PCI Clock Source |
| ICS650GI-41 | 功能描述:IC CLK SYNTHESIZER 16-TSSOP RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 產(chǎn)品變化通告:Product Discontinuation 04/May/2011 標(biāo)準(zhǔn)包裝:96 系列:- 類型:時(shí)鐘倍頻器，零延遲緩沖器 PLL:帶旁路 輸入:LVTTL 輸出:LVTTL 電路數(shù):1 比率 - 輸入:輸出:1:8 差分 - 輸入:輸出:無/無 頻率 - 最大:133.3MHz 除法器/乘法器:是/無 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:管件 其它名稱:23S08-5HPGG |
| ICS650GI-41LF | 功能描述:IC CLK SYNTHESIZER 16-TSSOP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 時(shí)鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無 頻率 - 最大:240MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應(yīng)商設(shè)備封裝:32-TQFP（7x7） 包裝:帶卷 (TR) |
| ICS650GI-41LFT | 功能描述:IC CLK SYNTHESIZER 16-TSSOP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 時(shí)鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無 頻率 - 最大:240MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應(yīng)商設(shè)備封裝:32-TQFP（7x7） 包裝:帶卷 (TR) |
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