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參數(shù)資料
| 型號： | ICS613M |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 157.5 MHz, OTHER CLOCK GENERATOR, PDSO16 |
| 封裝： | 0.150 INCH, SOIC-16 |
| 文件頁數(shù)： | 3/7頁 |
| 文件大?。?/td> | 230K |
| 代理商： | ICS613M |
LOW PHASE NOISE CLOCK MULTIPLIER
MDS 613 C
3
Revision 111204
Integrated Circuit Systems, Inc.
● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS613
External Component Selection
The ICS613 requires a minimum number of external
components for proper operation.
Decoupling Capacitors
Decoupling capacitors of 0.01
F should be connected
between VDD and GND pairs on pins 4 and 5, pins 6
and 8, pins 11 and 9, and pins 13 and 14 as close to
the ICS613 as possible. For optimum device
performance, the decoupling capacitors should be
mounted on the component side of the PCB. Avoid the
use of vias in the decoupling circuit.
Series Termination Resistor
When the PCB traces between the clock outputs and
the loads are over 1 inch, series termination should be
used. To series terminate a 50
trace (a commonly
used trace impedance) place a 33
resistor in series
with the clock line, as close to the clock output pin as
possible. The nominal impedance of the clock output is
20
.
Crystal Tuning Load Capacitors
The device crystal connections should include pads for
small capacitors from X1 to ground and from X2 to
ground. These capacitors are used to adjust the stray
capacitance of the board to match the nominally
required crystal load capacitance. Because load
capacitance can only be increased in this trimming
process, it is important to keep stray capacitance to a
minimum by using very short PCB traces (and no vias)
been the crystal and device. Crystal capacitors must be
connected from each of the pins X1 and X2 to ground.
The value (in pF) of these crystal caps should equal
(CL -6pF)*2. In this equation, CL= crystal load
capacitance in pF.
Example: For a crystal with a 16 pF load capacitance,
each crystal capacitor would be 20 pF [(16-6) x 2] = 20.
Reducing Jitter and Phase Noise
For applications that only require one output, jitter and
phase noise can be reduced by tying the unused
VDDO to ground. This will stop the output clock low
which will result in less switching noise on the active
output.
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS613. These ratings, which
are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the
device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Item
Rating
Supply Voltage, VDD
7V
All Inputs and Outputs
-0.5V to VDD+0.5V
Ambient Operating Temperature
0 to +70
°C
Storage Temperature
-65 to +150
°C
Soldering Temperature
260
°C
ICS613
LOW PHASE NOISE CLOCK MULTIPLIER
TSD
IDT / ICS LOW PHASE NOISE CLOCK MULTIPLIER
ICS613
3
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