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參數(shù)資料
| 型號： | ICS527R-01LFT |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 527 SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
| 封裝： | 0.150 INCH, 0.025 INCH PITCH, LEAD FREE, MO-153, SSOP-28 |
| 文件頁數(shù)： | 3/9頁 |
| 文件大?。?/td> | 176K |
| 代理商： | ICS527R-01LFT |
Clock Slicer User Configurable Zero Delay Buffer
MDS 527-01 E
3
Revision 032405
Integrated Circuit Systems, Inc.
● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS527-01
External Components
Decoupling Capacitors
As with any high performance mixed-signal IC, the
ICS527-01 must be isolated from system power supply
noise to perform optimally.
Decoupling capacitors of 0.01F must be connected
between each VDD and the PCB ground plane. The
capacitor must be connected close to the device to
minimize lead inductance.
Series Termination Resistor
Clock output traces over one inch should use series
termination. To series terminate a 50
trace (a
commonly used trace impedance), place a 33
resistor
in series with the clock line, as close to the clock output
pin as possible. The nominal impedance of the clock
output is 20
.
Using the Clock Slicer
First use DIV2 to select the function of the CLK2
output. If DIV2 is high, a divide-by-2, low skew version
of CLK1 is present on CLK2. If DIV2 is low, a SYNC
pulse is generated on CLK2. The SYNC pulse goes
high synchronously with the rising edges of ICLK and
CLK1 that are de-skewed. The SYNC function operates
at CLK1 frequencies up to 66 MHz. If neither CLK1/2 or
a SYNC pulse are required, then CLK2 should be
disabled by connecting OECLK2 to ground. This will
also give the lowest jitter on CLK1.
Next, the feedback scheme should be chosen. If CLK2
is being used as a SYNC pulse, or is tri-stated, then
CLK1 must be connected to FBIN. If CLK2 is selected
to be CLK1/2 (DIV2=1, OECLK2=1) then either CLK1
or CLK2 must be connected to FBIN. The choice
between CLK1 or CLK2 is illustrated by the following
examples where the device has been configured to
generate CLK1 that is twice the frequency on ICLK.
Using CLK1 as feedback will always result in
synchronized rising edges between ICLK and CLK1 if
CLK1 is used as feedback. CLK2 could be a falling
edge compared to ICLK. Therefore, wherever possible,
it is recommended to use CLK2 for feedback, which will
synchronize the rising edges of all three clocks.
More complicated feedback schemes can be used,
such as incorporating multiple output buffers in the
feedback path. An example is given later in the
datasheet. The fundamental property of the ICS527-01
is that it aligns rising edges on ICLK and FBIN at a ratio
determined by the reference and feedback dividers.
The drive strength is selected by the 2XDRIVE pin. If
high drive strength is required, we recommend tying
this pin low.
Lastly, the divider settings should be selected. This is
described in the following section.
Determining ICS527-01 Divider Settings
The user has full control in setting the desired output
clock over the range shown in the table on page 2. The
user should connect the divider select input pins
directly to ground (or VDD, although this is not required
because of internal pull-ups) during Printed Circuit
Board layout, so the ICS527-01 automatically produces
the correct clock when all components are soldered. It
is also possible to connect the inputs to parallel I/O
ports in order to switch frequencies.
The output of the ICS527-01 can be determined by the
following simple equation:
Where:
Reference Divider Word (RDW) = 0 to 127
Feedback Divider Word (FDW) = 0 to 127
ICLK
CLK1 Feedback
CLK1
CLK2
phase is
indeterminate
ICLK
CLK1
CLK2
CLK2 Feedback
FB Frequency
Input Frequency
FDW
2
+
RDW
2
+
------------------------
×
=
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ICS527R-01LFT | 527 SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
| ICS527R-01LF | 527 SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
| ICS527R-01 | 527 SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
| ICS527R-02I | 527 SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
| ICS527R-02T | 527 SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS527R-01T | 功能描述:IC CLOCK SLICER ZD BUFFER 28SSOP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 產(chǎn)品變化通告:Product Discontinuation 04/May/2011 標(biāo)準(zhǔn)包裝:96 系列:- 類型:時鐘倍頻器，零延遲緩沖器 PLL:帶旁路 輸入:LVTTL 輸出:LVTTL 電路數(shù):1 比率 - 輸入:輸出:1:8 差分 - 輸入:輸出:無/無 頻率 - 最大:133.3MHz 除法器/乘法器:是/無 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:管件 其它名稱:23S08-5HPGG |
| ICS527R-02 | 功能描述:IC CLOCK SLICER ZD BUFFER 28SSOP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 產(chǎn)品變化通告:Product Discontinuation 04/May/2011 標(biāo)準(zhǔn)包裝:96 系列:- 類型:時鐘倍頻器，零延遲緩沖器 PLL:帶旁路 輸入:LVTTL 輸出:LVTTL 電路數(shù):1 比率 - 輸入:輸出:1:8 差分 - 輸入:輸出:無/無 頻率 - 最大:133.3MHz 除法器/乘法器:是/無 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:管件 其它名稱:23S08-5HPGG |
| ICS527R-02I | 功能描述:IC CLOCK SLICER ZD BUFFER 28SSOP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:時鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
| ICS527R-02ILF | 制造商:Integrated Device Technology Inc 功能描述:IC CLOCK SLICER ZD BUFFER 28SSOP |
| ICS527R-02ILFT | 制造商:Integrated Device Technology Inc 功能描述:IC CLOCK SLICER ZD BUFFER 28SSOP |
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