參數(shù)資料
型號: ICS525RI-12T
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時鐘產(chǎn)生/分配
英文描述: 62.5 MHz, OTHER CLOCK GENERATOR, PDSO28
封裝: 0.150 INCH, MO-153, SSOP-28
文件頁數(shù): 1/10頁
文件大?。?/td> 232K
代理商: ICS525RI-12T
DATASHEET
USER CONFIGURABLE CLOCK
ICS525-01/02/11/12
IDT / ICS USER CONFIGURABLE CLOCK
1
ICS525-01/02/11/12 REV S 042407
Description
The ICS525-01/02/11/12 are the most flexible way to
generate a high-quality, high-accuracy, high-frequency
clock output from an inexpensive crystal or clock input.
The user can configure the device to produce nearly
any output frequency from any input frequency by
grounding or floating the select pins. Neither
microcontroller, software, nor device programmer are
needed to set the frequency. Using Phase-Locked Loop
(PLL) techniques, the device accepts a standard
fundamental mode, inexpensive crystal to produce
output clocks up to 250 MHz. It can also produce a
highly accurate output clock from a given input clock,
keeping them frequency locked together.
For similar capability with a serial interface, use the
ICS307. For simple multipliers to produce common
frequencies, refer to the ICS50x family of parts, which
are smaller and more cost effective.
These products are intended for clock generation. They
have low output jitter (variation in the output period), but
input to output skew and jitter are not defined nor
guaranteed. For applications which require defined
input to output timing, use the ICS527-01.
Features
Packaged as 28-pin SSOP (150 mil body)
Industrial and commercial versions available in Pb
(lead) free package
User determines the output frequency by setting all
internal dividers
Eliminates need for custom oscillators
No software needed
Online calculator determines register settings
Pull-ups on all select inputs
Input crystal frequency of 5 - 27 MHz
Input clock frequency of 2 - 50 MHz
Very low jitter
Duty cycle of 45/55 up to 200 MHz
Operating voltage of 3.0 V or 5.5 V
Ideal for oscillator replacement
Industrial temperature version available
For Zero Delay, refer to the ICS527
Block Diagram
VDD
GND
2
CLK
REF
Reference
Divider
Phase Comparator,
Charge Pump, and
Loop Filter
VCO
Divider
Output
Divider
9
73
R6:R0
V8:V0
S2:S0
X1/ICLK
X2
Crystal or clock
input
Optional crystal capacitors
Crystal
Oscillator
PD
相關PDF資料
PDF描述
ICS527R-03T PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), PDSO28
ICS527R-03 PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), PDSO28
ICS548G-06T 200 MHz, OTHER CLOCK GENERATOR, PDSO16
ICS548G-06LF 200 MHz, OTHER CLOCK GENERATOR, PDSO16
ICS548G-06LF 200 MHz, OTHER CLOCK GENERATOR, PDSO16
相關代理商/技術參數(shù)
參數(shù)描述
ICS527-01 制造商:ICS 制造商全稱:ICS 功能描述:Clock Slicer⑩ User Configurable Zero Delay Buffer
ICS527-02 制造商:ICS 制造商全稱:ICS 功能描述:Clock Slicer User Configurable PECL Input Zero Delay Buffer
ICS527-03 制造商:ICS 制造商全稱:ICS 功能描述:Clock Slicer User Configurable PECL Output Zero Delay Buffer
ICS527-04 制造商:ICS 制造商全稱:ICS 功能描述:Clock Slicer User Configurable PECL input Zero Delay Buffer
ICS527R-01 功能描述:IC CLOCK SLICER ZD BUFFER 28SSOP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器,PLL,頻率合成器 系列:- 產(chǎn)品變化通告:Product Discontinuation 04/May/2011 標準包裝:96 系列:- 類型:時鐘倍頻器,零延遲緩沖器 PLL:帶旁路 輸入:LVTTL 輸出:LVTTL 電路數(shù):1 比率 - 輸入:輸出:1:8 差分 - 輸入:輸出:無/無 頻率 - 最大:133.3MHz 除法器/乘法器:是/無 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP(0.173",4.40mm 寬) 供應商設備封裝:16-TSSOP 包裝:管件 其它名稱:23S08-5HPGG