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參數(shù)資料
| 型號(hào)： | ICS300M-11LFT |
| 元件分類(lèi)： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 135 MHz, OTHER CLOCK GENERATOR, PDSO8 |
| 封裝： | SOIC-8 |
| 文件頁(yè)數(shù)： | 1/4頁(yè) |
| 文件大?。?/td> | 54K |
| 代理商： | ICS300M-11LFT |
MDS300-11A
1
Revision 11118
Printed 11/10/98
Integrated Circuit Systems 1271 Parkmoor Ave.San JoseCA95126(408)295-9800tel(408)295-9818fax
PRELIMINARY
PRELIMINARY INFORMATION
INFORMATION
ICRO
CLOCK
ICS300-11
QTClock 125 MHz Clock Synthesizer
Packaged in 8 pin SOIC
Output clock frequency of 125 MHz at 3.3V
Input crystal or clock frequency of 20 MHz
Internal multiplier of 6.25
Quick turn frequency programming allows
production in two to four weeks
Low jitter - 20 ps one sigma typical
Duty cycle of 45/55
Full CMOS level outputs with 25 mA drive
capability at TTL levels
Tri-state output + PLL power down pin
Advanced, low power CMOS process
The ICS300-11 QTClock generates a high
quality, 125 MHz clock output from a 20 MHz
crystal or clock input. It is designed to replace
crystal oscillators in most electronic systems. The
ICS300 contains a One Time Programmable
(OTP) ROM which, in the -11 version, is factory
programmed with the PLL divider values to
output 125 MHz. Using Phase-Locked-Loop
(PLL) techniques, the device runs from a standard
fundamental mode, inexpensive crystal or clock. It
is smaller and less expensive than a single
125 MHz oscillator.
Block Diagram
Description
Features
125 MHz
Crystal
Oscillator
VDD GND
PLL
Clock
Synthesis
and Control
Circuitry
Output
Buffer
20 MHz crystal
or clock
X2
X1/ICLK
PDTS (output and PLL)
OTP
ROM
with PLL
Divider
Values
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