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參數(shù)資料
| 型號： | ICS300-MC6 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 300 Series CamclosureTM Camera System INTEGRATED CAMERA SYSTEM, INDOOR/OUTDOOR, WALL OR CEILING |
| 中文描述： | 300系列CamclosureTM攝像系統(tǒng)集成攝像系統(tǒng)，室內(nèi)/室外，墻壁或天花板 |
| 文件頁數(shù)： | 3/4頁 |
| 文件大?。?/td> | 64K |
| 代理商： | ICS300-MC6 |
MDS 300QT E
Integrated Circuit Systems, Inc. 525 Race Street San Jose CA95126(408) 295-9800tel www.icst.com
3
Revision 111000
ICS300/ICS301/ICS302
QTClock Quick Turn Clock Synthesizer
Parameter
ABSOLUTE MAXIMUM RATINGS (stresses beyond these can permanently damage the device)
Supply Voltage, VDD
Inputs
Clock Output
Ambient Operating Temperature
Soldering Temperature
Storage temperature
DC CHARACTERISTICS (VDD = 5.0V unless otherwise noted)
Operating Voltage, VDD
Input High Voltage, VIH, ICLK only
Input Low Voltage, VIL, ICLK only
Input High Voltage, VIH
Input Low Voltage, VIL
Output High Voltage, VOH
Output High Voltage, VOH
Output Low Voltage, VOL
IDD Operating Supply Current, 20 MHz crystal No Load, 100MHz
Short Circuit Current
On-Chip Pull-up Resistor, PDTS
Input Capacitance, PDTS
AC CHARACTERISTICS (VDD = 5.0V unless otherwise noted)
Input Frequency, crystal input, ICS300 and 301
Input Frequency, clock input, ICS300 and 301
Input Frequency, clock input, ICS302
Output Frequency, ICS300
Output Frequency, ICS300
Output Frequency, ICS301 and ICS302
Output Frequency, ICS301 and ICS302
Output Clock Rise Time
Output Clock Fall Time
Output Clock Duty Cycle (Note 1)
Absolute Clock Period Jitter
One Sigma Clock Period Jitter
Power-up time, PDTS goes high until Refer. out
Power-up time, PDTS goes high until CLK out
Conditions
Minimum
Typical
Maximum
Units
Referenced to GND
Referenced to GND
Referenced to GND
7
V
V
V
°C
°C
°C
-0.5
-0.5
0
VDD+0.5
VDD+0.5
70
260
150
Max of 10 seconds
-65
3
5.5
V
V
V
V
V
V
V
V
ICLK (Pin 1)
ICLK (Pin 1)
PDTS
PDTS
IOH=-4mA
IOH=-25mA
IOL=25mA
(VDD/2)+1
VDD/2
VDD/2
(VDD/2)-1
2
0.4
VDD-0.4
2.4
0.4
20
±70
270
4
mA
mA
k
pF
CLK output
Pin 7
Pin 7
5
2
50
6
6
6
6
27
50
125
160
100
200
200
55
MHz
MHz
MHz
MHz
MHz
MHz
MHz
ns
ns
%
ps
ps
ms
ms
VDD = 4.5 to 5.5V
VDD = 3.0 to 3.6V
VDD = 4.5 to 5.5V
VDD = 3.0 to 3.6V
0.8 to 2.0V
2.0 to 0.8V
at programmed level
Deviation from mean
1
1
45
49 to 51
±120
50
3
8
Reference on REF clk
10
20
Electrical Specifications
Note 1: These are typical values. The actual minimum and maximum duty cycle limits are shown on the
ICS300/301/302 QTClock Order Form for each programmed version.
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相關(guān)代理商/技術(shù)參數(shù) |
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| ICS300-MC8 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:300 Series CamclosureTM Camera System INTEGRATED CAMERA SYSTEM, INDOOR/OUTDOOR, WALL OR CEILING |
| ICS300MT | 制造商:ICS 制造商全稱:ICS 功能描述:QTClock⑩ Quick Turn Clock Synthesizer |
| ICS301M | 制造商:ICS 制造商全稱:ICS 功能描述:QTClock⑩ Quick Turn Clock Synthesizer |
| ICS301MT | 制造商:ICS 制造商全稱:ICS 功能描述:QTClock⑩ Quick Turn Clock Synthesizer |
| ICS302M | 制造商:ICS 制造商全稱:ICS 功能描述:QTClock⑩ Quick Turn Clock Synthesizer |
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