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ICS2572RevC090894
Integrated
Circuit
Systems, Inc.
ICS2572
User-Programmable Dual High-Performance Clock Generator
Block Diagram
XTAL1
XTAL2
Crystal
Oscillator
Reference
Divider
Charge
Pump
Phase-
Frequency
Comparator
EXTFREQ
VCO
Prescaler
/ M
Strobe
FS0
FS1
FS2
FS3
MS0
MS1
/ A
MCLK PLL (as above)
VCLK Set &
Program
Mode
Interface
MCLK Set
/ 2
/ 4
/ 8
/ 2
/ 4
MCLK
CLK-
CLK+
LOAD
/1, 4, 5 or 8
/ 8
Description
The ICS2572 is a dual-PLL (phase-locked loop) clock gener-
ator with differential video outputs specifically designed for
high-resolution, high-refresh rate, video applications. The
video PLL generates any of 16 pre-programmed frequencies
through selection of the address lines FS0-FS3. Similarly, the
auxiliary PLL can generate any one of four pre-programmed
frequencies via the MS0 & MS1 lines.
A unique feature of the ICS2572 is the ability to redefine
frequency selections after power-up. This permits complete
set-up of the frequency table upon system initialization.
Features
Advanced ICS monolithic phase-locked loop
technology
Supports high-resolution graphics - differential CLK out-
put to 185 MHz
Divided dotclock output (LOAD) available
Simplified device programming
Sixteen selectable VCLK frequencies (all user
re-programmable)
Four selectable MCLK frequencies (all user
re-programmable)
Windows NT compatible
Applications
High end PC/low end workstation graphics designs
requiring differential output
X Terminal graphics
E-95