參數(shù)資料
型號: ICS251PMT
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 7/10頁
文件大?。?/td> 0K
描述: IC CLK SYNTHESIZER FP SGL 8-SOIC
標(biāo)準(zhǔn)包裝: 2,500
系列: VersaClock™
類型: 時鐘/頻率合成器,擴(kuò)展頻譜時鐘發(fā)生器
PLL:
輸入: 時鐘,晶體
輸出: CMOS
電路數(shù): 1
比率 - 輸入:輸出: 1:1
差分 - 輸入:輸出: 無/無
頻率 - 最大: 200MHz
除法器/乘法器: 是/無
電源電壓: 3.15 V ~ 3.45 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 8-SOIC
包裝: 帶卷 (TR)
其它名稱: 251PMT
ICS251
FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER
EPROM CLOCK SYNTHESIZER
IDT FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER
6
ICS251
REV D 030212
AC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V ±5%, Ambient Temperature -40 to +85
° C
Note 1: Measured with 15 pF load.
Note 2: Duty Cycle is configuration dependent. Most configurations are minimum 45% and maximum 55%.
Thermal Characteristics
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Input Frequency
FIN
Fundamental Crystal
5
27
MHz
Input Clock
3
150
MHz
Output Frequency
0.314
200
MHz
Output Rise Time
tOR
20% to 80%, Note 1
1
ns
Output Fall Time
tOF
80% to 20%, Note 1
1
ns
Duty Cycle
Note 2
40
49-51
60
%
Power-up time
PLL lock time from
power-up
410
ms
PDTS goes high until
stable CLK output,
Spread Spectrum Off
.6
2
ms
PDTS goes high until
stable CLK output,
Spread Spectrum On
47
ms
PDTS goes high until
spread spectrum is
stable, Spread Spectrum
On
10
50
ms
One Sigma Clock Period Jitter
Configuration Dependent
50
ps
Maximum Absolute Jitter
tja
Deviation from Mean.
Configuration Dependent
+200
ps
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Thermal Resistance Junction to
Ambient
θJA
Still air
150
° C/W
θJA
1 m/s air flow
140
° C/W
θJA
3 m/s air flow
120
° C/W
Thermal Resistance Junction to Case
θJC
40
° C/W
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