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參數(shù)資料
| 型號： | ICS251PMLFT |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 4/10頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLK SYNTHESIZER FP SGL 8-SOIC |
| 標準包裝： | 2,500 |
| 系列： | VersaClock™ |
| 類型： | 時鐘/頻率合成器，擴展頻譜時鐘發(fā)生器 |
| PLL： | 是 |
| 輸入： | 時鐘，晶體 |
| 輸出： | CMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:1 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 200MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.15 V ~ 3.45 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應商設(shè)備封裝： | 8-SOIC |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 251PMLFT |
ICS251
FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER
EPROM CLOCK SYNTHESIZER
IDT FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER
3
ICS251
REV D 030212
2) The external crystal should be mounted just next to the
device with short traces. The X1 and X2 traces should not
be routed next to each other with minimum spaces, instead
they should be separated and away from other traces.
3) To minimize EMI, the 33
Ω series termination resistor (if
needed) should be placed close to the clock output.
4) An optimum layout is one with all components on the
same side of the board, minimizing vias through other signal
layers. Other signal traces should be routed away from the
ICS251. This includes signal traces just underneath the
device, or on layers adjacent to the ground plane layer used
by the device.
ICS251 Configuration Capabilities
The architecture of the ICS251 allows the user to easily
configure the device to a wide range of output frequencies,
for a given input reference frequency.
The frequency multiplier PLL provides a high degree of
precision. The M/N values (the multiplier/divide values
available to generate the target VCO frequency) can be set
within the range of M = 1 to 2048 and N = 1 to 1024.
The ICS251 also provides separate output divide values,
from 2 through 20, to allow the two output clock banks to
support widely differing frequency values from the same
PLL.
Each output frequency can be represented
as:
Output Drive Control
The ICS251 has two output drive settings. Low drive should
be selected when outputs are less than 100 MHz. High drive
should be selected when outputs are greater than 100 MHz.
(Consult the AC Electrical Characteristics for output rise and
fall times for each drive option.)
ICS VersaClock Software
ICS applies years of PLL optimization experience into a user
friendly software that accepts the user’s target reference
clock and output frequencies and generates the lowest jitter,
lowest power configuration, with only a press of a button.
The user does not need to have prior PLL experience or
determine the optimal VCO frequency to support multiple
output frequencies.
VersaClock software quickly evaluates accessible VCO
frequencies with available output divide values and provides
an easy to understand, bar code rating for the target output
frequencies. The user may evaluate output accuracy,
performance trade-off scenarios in seconds.
Spread Spectrum Modulation
The ICS251 utilizes frequency modulation (FM) to distribute
energy over a range of frequencies. By modulating the
output clock frequencies, the device effectively lowers
energy across a broader range of frequencies; thus,
lowering a system’s electro-magnetic interference (EMI).
The modulation rate is the time from transitioning from a
minimum frequency to a maximum frequency and then back
to the minimum.
Spread Spectrum Modulation can be applied as either
“center spread” or “down spread”. During center spread
modulation, the deviation from the target frequency is equal
in the positive and negative directions. The effective
average frequency is equal to the target frequency. In
applications where the clock is driving a component with a
maximum frequency rating, down spread should be applied.
In this case, the maximum frequency, including modulation,
is the target frequency. The effective average frequency is
less than the target frequency.
The ICS251 operates in both center spread and down
spread modes. For center spread, the frequency can be
modulated between +/- 0.125% to +/-2.0%. For down
spread, the frequency can be modulated between -0.25% to
-4.0%.
Both output frequency banks will utilize identical spread
spectrum percentage deviations and modulation rates, if a
common VCO frequency can be identified.
Spread Spectrum Modulation Rate
The spread spectrum modulation frequency applied to the
output clock frequency may occur at a variety of rates. For
applications requiring the driving of “down-circuit” PLLs,
Zero Delay Buffers, or those adhering to PCI standards, the
spread spectrum modulation rate should be set to 30-33
kHz. For other applications, a 120 kHz modulation option is
available.
OutputFreq
REFFreq
OutputDivide
--------------------------------------
M
N
-----
=
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| VI-J1J-MZ-F1 | CONVERTER MOD DC/DC 36V 25W |
| ICS251PMILFT | IC CLK SYNTHESIZER FP SGL 8-SOIC |
| VI-J13-MZ-F1 | CONVERTER MOD DC/DC 24V 25W |
| VE-J13-MZ-F4 | CONVERTER MOD DC/DC 24V 25W |
| VE-J13-MZ-F3 | CONVERTER MOD DC/DC 24V 25W |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS251PMT | 功能描述:IC CLK SYNTHESIZER FP SGL 8-SOIC RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:VersaClock™ 標準包裝:2,000 系列:- 類型:PLL 時鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無 頻率 - 最大:240MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應商設(shè)備封裝:32-TQFP（7x7） 包裝:帶卷 (TR) |
| ICS252 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:FIELD PROGRAMMABLE DUAL OUTPUT SS VERSACLOCK SYNTHESIZER |
| ICS252MI-52LF | 制造商:Integrated Device Technology Inc 功能描述:IC CLK SYNTHESIZER PLL 8SOIC 制造商:Integrated Device Technology Inc 功能描述:IC CLK SYNTHESIZER FP DUAL 8SOIC |
| ICS252MI-52LFT | 制造商:Integrated Device Technology Inc 功能描述:IC CLK SYNTHESIZER PLL 8SOIC 制造商:Integrated Device Technology Inc 功能描述:IC CLK SYNTHESIZER FP DUAL 8SOIC |
| ICS252MIP | 制造商:ICS 制造商全稱:ICS 功能描述:Field Programmable Dual Output SS VersaClock Synthesizer |
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