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參數(shù)資料
| 型號(hào)： | ICS2510CGLF-T |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24 |
| 封裝： | 0.173 INCH, MO-153, TSSOP-24 |
| 文件頁數(shù)： | 1/7頁 |
| 文件大?。?/td> | 94K |
| 代理商： | ICS2510CGLF-T |
Integrated
Circuit
Systems, Inc.
General Description
Features
ICS2510C
0010E—03/31/03
Block Diagram
3.3V Phase-Lock Loop Clock Driver
Pin Configuration
The ICS2510C is a high performance, low skew, low jitter
clock driver. It uses a phase lock loop (PLL) technology to
align, in both phase and frequency, the CLKIN signal with
the CLKOUT signal. It is specifically designed for use with
synchronous SDRAMs. The ICS2510C operates at 3.3V
VCC and drives up to ten clock loads.
One bank of ten outputs provide low-skew, low-jitter
copies of CLKIN. Output signal duty cycles are adjusted
to 50 percent, independent of the duty cycle at CLKIN.
Outputs can be enabled or disabled via control (OE)
inputs. When the OE inputs are high, the outputs align in
phase and frequency with CLKIN; when the OE inputs are
low, the outputs are disabled to the logic low state.
The ICS2510C does not require
external RC filter
components.The loop filter for the PLL is included on-chip,
minimizing component count, board space, and cost.The
test mode shuts off the PLL and connects the input
directly to the output buffer.This test mode, the ICS2510C
can be use as low skew fanout clock buffer device. The
ICS2510C comes in 24 pin 173mil Thin Shrink Small-
Outline package (TSSOP) package.
Meets or exceeds PC133 registered DIMM
specification1.1
Spread Spectrum Clock Compatible
Distributes one clock input to one bank of ten outputs
Operating frequency 25MHz to 175MHz
External feedback input (FBIN) terminal is used to
synchrionize the outputs to the clock input
No external RC network required
Operates at 3.3V Vcc
Plastic 24-pin 173mil TSSOP package
FBIN
CLKIN
AVCC
OE
PLL
CLK1
CLK0
FBOUT
CLK2
CLK3
CLK4
CLK5
CLK6
CLK7
CLK8
CLK9
AGND
VCC
CLK0
CLK1
CLK2
GND
CLK3
CLK4
VCC
OE
FBOUT
CLKIN
AVCC
VCC
CLK9
CLK8
GND
CLK7
CLK6
CLK5
VCC
FBIN
ICS2510C
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
24 Pin TSSOP
4.40 mm. Body, 0.65 mm. pitch
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS2510CGT | 功能描述:IC CLOCK DVR PLL 3.3V 24-TSSOP RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 時(shí)鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無 頻率 - 最大:240MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應(yīng)商設(shè)備封裝:32-TQFP（7x7） 包裝:帶卷 (TR) |
| ICS2510CG-T | 制造商:ICS 制造商全稱:ICS 功能描述:3.3V Phase-Lock Loop Clock Driver |
| ICS2510CGT-CQ0 | 功能描述:IC CLOCK DVR PLL 3.3V 24-TSSOP RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 時(shí)鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無 頻率 - 最大:240MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應(yīng)商設(shè)備封裝:32-TQFP（7x7） 包裝:帶卷 (TR) |
| ICS251MI-XX | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER |
| ICS251MI-XXLF | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER |
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