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參數(shù)資料
| 型號(hào)： | ICS2509GLF |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 2509 SERIES, PLL BASED CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24 |
| 封裝： | 0.173 INCH, TSSOP-24 |
| 文件頁數(shù)： | 1/7頁 |
| 文件大?。?/td> | 200K |
| 代理商： | ICS2509GLF |
Integrated
Circuit
Systems, Inc.
General Description
Features
ICS2509
Advance Information
Block Diagram
3.3V Phase-Lock Loop Clock Driver
2509 Rev - 4/20/99
Pin Configuration
24 Pin TSSOP
ADVANCE INFORMATION documents contain information on products
in the formative or design phase development. Characteristic data and
other specifications are design goals. ICS reserves the right to change or
discontinue these products without notice.
The ICS2509 is a high performance, low skew, low jitter
clock driver. It uses a phase lock loop (PLL) technology to
align, in both phase and frequency, the CLKIN signal with
the CLKOUT signal. It is specifically designed for use with
synchronous SDRAMs. The ICS2509 operates at 3.3V VCC
and drive up to nine clock loads.
One bank of five outputs and one bank of four outputs provide
nine low-skew, low-jitter copies of CLKIN. Output signal
duty cycles are adjusted to 50 percent, independent of the
duty cycle at CLKIN. Each bank of outputs can be enabled or
disabled separately via control (OEA and OEB) inputs. When
the OE inputs are high, the outputs align in phase and
frequency with CLKIN; when the OE inputs are low, the
outputs are disabled to the logic low state.
The ICS2509 does not require external RC filter components.
The loop filter for the PLL is include on-chip, minimizing
component count, board space, and cost. The buffer mode
shuts off the PLL and connects the input directly to the
output buffer. This buffer mode, the ICS2509 can be use as
low skew fanout clock buffer device. The ICS2509 comes in
24 pin 173mil Thin Shrink Small-Outline package (TSSOP)
package.
Meet PC SDRAM Registered DIMM Specification
Spread Spectrum Clock Compatible
Distributes one clock input to one bank of five and one
bank of four outputs
Separate output enable(OEA,OEB) for each output bank
Operating frequency 25 MHz to 150 Mhz
External feedback input (FBIN) terminal is used to
synchrionize the outputs to the clock input
No external RC network required
Operates at 3.3V Vcc
Plastic 24-pin 173mil TSSOP package
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS251 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER |
| ICS2510C | 制造商:ICS 制造商全稱:ICS 功能描述:3.3V Phase-Lock Loop Clock Driver |
| ICS2510CG | 功能描述:IC CLOCK DVR PLL 3.3V 24-TSSOP RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 時(shí)鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無 頻率 - 最大:240MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應(yīng)商設(shè)備封裝:32-TQFP（7x7） 包裝:帶卷 (TR) |
| ICS2510CGLF | 功能描述:IC CLOCK DVR PLL 3.3V 24-TSSOP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 時(shí)鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無 頻率 - 最大:240MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應(yīng)商設(shè)備封裝:32-TQFP（7x7） 包裝:帶卷 (TR) |
| ICS2510CGLFT | 功能描述:IC CLOCK DVR PLL 3.3V 24-TSSOP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 時(shí)鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無 頻率 - 最大:240MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應(yīng)商設(shè)備封裝:32-TQFP（7x7） 包裝:帶卷 (TR) |
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