參數(shù)資料
型號： ICS1893AFILF
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 98/136頁
文件大?。?/td> 0K
描述： PHYCEIVER LOW PWR 3.3V 48-SSOP
標(biāo)準(zhǔn)包裝： 30
系列： PHYceiver™
類型： PHY 收發(fā)器
規(guī)程： MII
電源電壓： 3.14 V ~ 3.47 V
安裝類型： 表面貼裝
封裝/外殼： 48-BSSOP（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 48-SSOP
包裝： 管件
其它名稱： 1893AFILF
ICS1893AF, Rev D 10/26/04
October, 2004
64
Chapter 8
Management Register Set
ICS1893AF Data Sheet - Release
Copyright 2004, Integrated Circuit Systems, Inc.
All rights reserved.
8.3.2
100Base-TX Full Duplex (bit 1.14)
The STA reads this bit to learn if the ICS1893AF can support 100Base-TX, full-duplex operations. The
ISO/IEC specification requires that the ICS1893AF must set bit 1.14 to logic:
Zero if it cannot support 100Base-TX, full-duplex operations.
One if it can support 100Base-TX, full-duplex operations. (For the ICS1893AF, the default value of bit
1.14 is logic one, in that the ICS1893AF supports 100Base-TX, full-duplex operations.)
Bit 1.14 is a Command Override Write bit, which allows an STA to alter the default value of this bit. [See the
description of bit 16.15, the Command Override Write Enable bit, in Section 8.11, “Register 16: Extended
8.3.3
100Base-TX Half Duplex (bit 1.13)
The STA reads this bit to learn if the ICS1893AF can support 100Base-TX, half-duplex operations. The
ISO/IEC specification requires that the ICS1893AF must set bit 1.13 to logic:
Zero if it cannot support 100Base-TX, half-duplex operations.
One if it can support 100Base-TX, half-duplex operations. (For the ICS1893AF, the default value of bit
1.13 is logic one. Therefore, when an STA reads the Status Register, the STA is informed that the
ICS1893AF supports 100Base-TX, half-duplex operations.)
This bit 1.13 is a Command Override Write bit, which allows an STA to alter the default value of this bit.
[See the description of bit 16.15, the Command Override Write Enable bit, in Section 8.11, “Register 16:
8.3.4
10Base-T Full Duplex (bit 1.12)
The STA reads this bit to learn if the ICS1893AF can support 10Base-T, full-duplex operations. The
ISO/IEC specification requires that the ICS1893AF must set bit 1.12 to logic:
Zero if it cannot support 10Base-T, full-duplex operations.
One if it can support 10Base-T, full-duplex operations. (For the ICS1893AF, the default value of bit 1.12
is logic one. Therefore, when an STA reads the Status Register, the STA is informed that the ICS1893AF
supports 10Base-T, full-duplex operations.)
This bit 1.12 is a Command Override Write bit, which allows an STA to alter the default value of this bit.
[See the description of bit 16.15, the Command Override Write Enable bit, in Section 8.11, “Register 16:
8.3.5
10Base-T Half Duplex (bit 1.11)
The STA reads this bit to learn if the ICS1893AF can support 10Base-T, half-duplex operations. The
ISO/IEC specification requires that the ICS1893AF must set bit 1.11 to logic:
Zero if it cannot support 10Base-T, half-duplex operations.
One if it can support 10Base-T, half-duplex operations. (For the ICS1893AF, the default value of bit 1.11
is logic one. Therefore, when an STA reads the Status Register, the STA is informed that the ICS1893AF
supports 10Base-T, half-duplex operations.)
Bit 1.11 of the ICS1893AF Status Register is a Command Override Write bit., which allows an STA to alter
the default value of this bit. [See the description of bit 16.15, the Command Override Write Enable bit, in
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ICS1893AFILFT 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:PHYceiver™ 標(biāo)準(zhǔn)包裝:250 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR)
ICS1893AFIT 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:PHYceiver™ 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR)
ICS1893AFLF 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:PHYceiver™ 標(biāo)準(zhǔn)包裝:1 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):1/1 規(guī)程:RS422，RS485 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:14-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:14-SOICN 包裝:剪切帶 (CT) 其它名稱:ISL31470EIBZ-T7ACT
ICS1893AFLFT 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:PHYceiver™ 標(biāo)準(zhǔn)包裝:250 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR)
ICS1893AFT 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:PHYceiver™ 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR)
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