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參數(shù)資料
| 型號(hào)： | ICS1567M-XXX-LF |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 180 MHz, VIDEO CLOCK GENERATOR, PDSO16 |
| 封裝： | 0.300 INCH, SOIC-16 |
| 文件頁(yè)數(shù)： | 10/11頁(yè) |
| 文件大?。?/td> | 161K |
| 代理商： | ICS1567M-XXX-LF |
AC Characteristics
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
CLK and CLK TIMING
Duty Cycle
THIGH
40
60
%
3, 4, 9
Frequency Error
0.5
%
Rise Time
Tr
2ns
5, 9
Fall Time
Tf
2ns
5, 9
VCO Frequency
FVCO
20
180
MHz
1
PLL Acquire Time
TLOCK
500
uS
LD* TIMING
Duty Cycle
THIGH
40
60
%
6
Load Frequency
FLOAD
60
MHz
Rise Time
Tr
2ns
7, 8
Fall Time
Tf
2ns
7, 8
REFERENCE INPUT CLOCK
Crystal Frequency
FXTAL
520
MHz
Crystal Oscillator
CPAR
20
pF
Loading Capacitance
XTAL1 High Time
TXHI
8ns
2
XTAL1 Low Time
TXLO
8ns
2
Rise Time
Tr
10
ns
2, 7
Fall Time
Tf
10
ns
2, 7
DIGITAL INPUTS
Frequency Select Setup Time
110
ns
10
Frequency Select Hold Time
210
ns
10
Strobe Pulse Width
320
ns
10
PIPELINE DELAY RESET
Reset Activation
42*TCLK
ns
10
Reset Duration
5
4*TCLK
ns
10
Restart Delay
6
-1*TCLK
+1.5*TCLK
ns
10
Notes:
1.
Use of the post-divider is required for frequencies lower than 20 MHz on CLK and CLK outputs. Use of the
post-divider is recommended for output frequencies lower than 65 MHz.
2.
Values for XTAL1 driven by an external clock
3.
Duty Cycle for Differential Output (CLK- CLK)
4.
Duty cycle measured at VOD/2 for Differential CLK Output
5.
Rise and fall time between 20% and 80% of VOD
6.
Duty cycle measured at 1.4V for TTL I/O
7.
Rise and fall time between 0.8 and 2.0 VDC for TTL I/O
8.
Output pin loading = 15 pF
9.
See Figure 3.
10. See Figure 4.
ICS1567
8
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