- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄67684 > ICS1524AMT 250 MHz, OTHER CLOCK GENERATOR, PDSO24 PDF資料下載
參數(shù)資料
| 型號： | ICS1524AMT |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 250 MHz, OTHER CLOCK GENERATOR, PDSO24 |
| 封裝： | 0.300INCH, SOIC-24 |
| 文件頁數(shù)： | 23/24頁 |
| 文件大小： | 354K |
| 代理商： | ICS1524AMT |
ICS1524A
8
ICS1524A Rev D 12/23/2005
Name:
Feedback Divider 0 Register / Feedback Divider 1 Register
Register:
2h, 3h
Index:
Read / Write*
Bit Name
Index
Bit #
Reset Value
Description
FBD 0-7
2
0 -7
FF
PLL Feedback Divider LSBs (0 -7).* When Bit 0 = 0, then the total
number of clocks per line is even. When Bit 0 = 1, then the total
number of clocks is odd.
FBD 8 -11
3
0 -3
F
PLL Feedback Divider MSBs (8 -11)*
Reserved
3
4 -7
Reserved
Feedback Divider Modulus
=
*Double-buffered registers. Actual working registers are loaded during software PLL reset.
See Register 8h for details.
Name:
DPA Offset Register
Register:
4h
Index:
Read / Write
Bit Name
Bit #
Reset Value
Description
DPA_OS0-5
0 - 5
0
Dynamic Phase Adjust Offset
Reserved
6
0
Reserved
Fil_Sel
7
0
Loop Filter Select
Bit
Name
Description
0-5
DPA_OS0-5
Dynamic Phase Adjust Offset.
Selects clock edge offset in discrete steps from zero to one clock period minus one step.
Resolution (number of delay elements per clock cycle) is selected by DPA_Res0-1 (Reg 5:0-1).
Note: Offsets equal to or greater than one clock period are neither recommended nor supported.
Example: For DPA_Res0-1=01H, the clock can be delayed from 0 to 31 steps.
7
Fil_Sel
Selects external loop filter (0) or internal loop filter (1).
The use of an external loop filter is strongly recommended for all designs. Typical loop filter
values are 6.8K Ohms for the series resistor, 3300 pF RF-type capacitor for the series capacitor,
and 33 pF for the shunt capacitor.
12
≤ Feedback Divider Modulus ≤ 4103
The value that is programmed into these two registers, plus a value of 8, defines the total number of clock periods that the ICS
1524 generates between HSYNCs. Program these registers with the total number of horizontal clocks per line minus 8.
3
g
e
R2
g
e
R
32
1
0
7
65
4
32
1
0
+8
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ICS1527G-60LFTR | PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| ICS1562BM-001LF | 260 MHz, VIDEO CLOCK GENERATOR, PDSO16 |
| ICS1567M-XXX-LF | 180 MHz, VIDEO CLOCK GENERATOR, PDSO16 |
| ICS1574BM | 130 MHz, VIDEO CLOCK GENERATOR, PDSO16 |
| ICS1890Y-14 | 1 CHANNEL(S), 100M bps, SERIAL COMM CONTROLLER, PQFP64 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS1524M | 制造商:ICS 制造商全稱:ICS 功能描述:Dual Output Phase Controlled SSTL-3/PECL Clock Generator |
| ICS1524MT | 制造商:ICS 制造商全稱:ICS 功能描述:Dual Output Phase Controlled SSTL-3/PECL Clock Generator |
| ICS1526 | 制造商:ICS 制造商全稱:ICS 功能描述:Video Clock Synthesizer |
| ICS1526G | 功能描述:IC VIDEO CLK SYNTHESIZER 16TSSOP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 產(chǎn)品變化通告:Product Discontinuation 04/May/2011 標準包裝:96 系列:- 類型:時鐘倍頻器，零延遲緩沖器 PLL:帶旁路 輸入:LVTTL 輸出:LVTTL 電路數(shù):1 比率 - 輸入:輸出:1:8 差分 - 輸入:輸出:無/無 頻率 - 最大:133.3MHz 除法器/乘法器:是/無 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:管件 其它名稱:23S08-5HPGG |
| ICS1526GILF | 功能描述:IC VIDEO CLK SYNTHESIZER 16TSSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:1,000 系列:Precision Edge® 類型:時鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應(yīng)商設(shè)備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。