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參數(shù)資料
| 型號(hào)： | ICPL2533 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | PC Board Connector; No. of Contacts:36; Pitch Spacing:0.1"; No. of Rows:2; Mounting Type:PCB Straight Thru Hole; Contact Material:Copper Alloy; Gender:Female; Leaded Process Compatible:No; Peak Reflow Compatible (260 C):No RoHS Compliant: No |
| 中文描述： | 高速雙通道光電晶體管的光耦合隔離器輸出 |
| 文件頁(yè)數(shù)： | 3/4頁(yè) |
| 文件大小： | 66K |
| 代理商： | ICPL2533 |
SWITCHING SPECIFICATIONS AT T
A
= 25°C ( V
CC
= 5V Unless otherwise noted )
0
I
F
V
O
1.3V
1.3V
5V
t
PHL
t
PLH
V
OL
DB91038-AAS/A3
7/12/00
2
I
F
Monitor
100
R
L
V
O
C
L
= 15pF
8
7
6
5
I
F
1
4
3
10% Duty Cycle
1/f < 100
μ
s
5V
PARAMETER
SYM DEVICE
MIN TYP MAX UNITS TEST CONDITION
0.8
1.5
μ
s
I
F
= 8mA,R
= 7.5k
(note 10 )
Propagation Delay Time
to
Logic Low at Output ( fig 1 )
t
PHL
0.3
1.5
μ
s
I
F
= 16mA,R
= 4.7k
,
(note11 )
1.0
2.5
μ
s
I
F
= 8mA,R
= 7.5k
,
(note 10 )
Propagation Delay Time
to
Logic High at Output ( fig 1 )
t
PLH
1.1
2.5
μ
s
I
F
= 16mA,R
= 4.7k
,
(note11 )
1000
V/
μ
s
I
F
= 0mA, V
= 10V
PP
R
L
= 7.5k
,
(note9,10 )
Common Mode Transient
Immunity at Logic High
Level Output ( fig 2 )
CM
H
1000
V/
μ
s
I
F
= 0mA, V
= 10V
R
L
= 4.7k
,
(note9,11 )
-1000
V/
μ
s
I
F
= 8mA,V
CM
= 10V
PP
R
L
= 7.5k
,
Common Mode Transient
Immunity at Logic Low
Level Output ( fig 2 )
CM
L
-1000
V/
μ
s
I
F
= 16mA,V
= 10V
PP
R
L
= 1.9k
,
(note9,11 )
NOTES:-
1.
2.
3.
4.
5.
6.
Derate linearly above 70
o
C free air temperature at a rate of 0.8 mA/°C.
Derate linearly above 70
o
C free air temperature at a rate of 1.6 mA/°C.
Derate linearly above 70
o
C free air temperature at a rate of 0.9 mW/°C.
Derate linearly above 70
o
C free air temperature at a rate of 1.0 mW/°C.
Each channel.
CURRENT TRANSFER RATIO is defined as the ratio of output collector current,I
O
, to the forward LED
input current, I
F
times 100%.
Device considered a two-terminal device: pins 1,2,3,and 4 shorted together and pins 5,6,7,and 8 shorted
together.
Measured between pins 1 and 2 shorted together, and pins 3 and 4 shorted together.
Common mode transient immunity in Logic High level is the maximum tolerable (positive) dVcm/dt on
the leading edge of the common mode pulse V
to assure that the output will remain in a Logic High
state (i.e. V
> 2.0V). Common mode transient immunity in Logic Low level is the maximum tolerable
(negative) dVcm/dt on the trailing edge of the common mode pulse signal, V
CM
to assure that the output
will remain in Logic Low state (i.e. V
O
< 0.8V).
10. The 7.5k
load represents 1 LSTTL unit load of 0.36mA and a 20k
pull-up resistor.
11. The 4.7k
load represents 1 LSTTL unit load of 0.36mA and a 8.2k
pull-up resistor.
12. The 2500 V
RMS
/ 1minute capability is validated by a factory 3.1k V
RMS
/ 1 second dielectric test.
7.
8.
9.
FIG.1 SWITCHING TEST CIRCUIT
PULSE
GENERATOR
Z
= 50
t
r
= 5ns
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