11
negative excursions which could damage the device, and is
only necessary with certain high spped amplifiers. For
applications where the output reference ground point is
established somewhere other than at the DAC, the circuit of
Figure 9 can be used. Here, op-amp A
2
removes the slight
error due to IR voltage drop between the internal Analog
GrouND node and the external ground connection. For
13-bit or lower accuracy, omit A
2
and connect AGND
F
and
AGND
S
directly to ground through as low a resistance as
possible.
Zero Offset Adjustment
1. Connect all data inputs and WR, CS, A
0
and A
1
to
DGND.
2. Adjust offset zero-adjust trim-pot of the operational ampli-
fier A
2
, if used, for a maximum of 0V
±
50
μ
V at AGND
S
.
3. Adjust the offset zero-adjust trim-pot of the output
op-amp, A
1
, for a maximum of 0V
±
50
μ
V at V
OUT
.
Gain Adjustment (Optional)
1. Connect all data inputs to V+, connect WR, CS, A
0
and A
1
to DGND.
2. Monitor V
OUT
for a -V
REF
(1 - 1/2
14
) reading.
3. To decrease V
OUT
, connect a series resistor of 5
or less
between the reference voltage and the V
RFM
and V
RFL
terminals (pins 20 and 18).
4. To increase V
OUT
, connect a series resistor of 5
or less
between A
1
output and the R
FB
terminal (pin 21).
Bipolar (2’s Complement) Operation (ICL7134B)
The circuit configuration for bipolar mode operation
(ICL7134B) is shown in Figure 10. Using 2’s complement
digital input codes and positive and negative reference
voltage values, four-quadrant multiplication is obtained. The
“digital input code/analog output value” table for bipolar
mode is given in Table 3. Amplifier A
3
, together with internal
resistors R
INV1
and R
INV2
, forms a simple voltage inverter
circuit. The MSB ladder leg sees a reference input of
approximately -V
REF
, so the MSB’s weight is reversed from
the polarity of the other bits. In addition, the ICL7134B’s
feedback resistance is switched to 2R under PROM control,
so that the bipolar output range is +V
REF
to -V
REF
(1 -
1/2
13
). Again, the grounding arrangement of Figure 9 can be
used if necessary.
FIGURE 8. UNIPOLAR BINARY, TWO-QUADRANT
MULTIPLYING CIRCUIT
FIGURE 9. UNIPOLAR BINARY OPERATION WITH FORCED
GROUND
TABLE 2. CODE TABLE - UNIPOLAR BINARY OPERATION
DIGITAL INPUT
ANALOG OUTPUT
-V
REF
(1 - 1/2
14
)
-V
REF
(1/2 + 1/2
14
)
1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 0 0 0 0 0 0 0 0 0 0 0 0 1
1 0 0 0 0 0 0 0 0 0 0 0 0 0
-V
REF
/2
-V
REF
(1/2 - 1/2
14
)
-V
REF
(1/2
14
)
0 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0
0
TABLE 3. CODE TABLE - BIPOLAR (2’S COMPLEMENT)
OPERATION
DIGITIAL INPUT
ANALOG OUTPUT
-V
REF
(1 - 1/2
13
)
-V
REF
(1/2
13
)
0 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0
0
V
REF
(1/2
13
)
V
REF
(1 - 1/2
13
)
1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 0 0 0 0 0 0 0 0 0 0 0 0 1
1 0 0 0 0 0 0 0 0 0 0 0 0 0
V
REF
ICL7134