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參數(shù)資料
| 型號： | ICL7121LCJI |
| 廠商： | INTERSIL CORP |
| 元件分類： | DAC |
| 英文描述： | 16-Bit Multiplying Microprocessor-Compatible D/A Converter |
| 中文描述： | PARALLEL, WORD INPUT LOADING, 1.8 us SETTLING TIME, 16-BIT DAC, CDIP28 |
| 封裝： | CERAMIC, DIP-28 |
| 文件頁數(shù)： | 8/10頁 |
| 文件大小： | 607K |
| 代理商： | ICL7121LCJI |
8
Amplifier A
1
is the output amplifier. An additional amplifier
A
2
may be used to force AGND
F
if the ground reference
piont is established elsewhere that at the DAC, as in Figure
2.
A feedback compensation capacitor, C
F
, improves the
settling time by reducing ringing. This capacitor is normally in
the 10pF - 40pF range, depending on layout and the output
amplifier selected. If C
F
is too small, rigning or oscillation
can occur when using an op amp with a high gain
bandwidth. If C
F
is too large, the response of the output
amplifier will be overdamped and will settle slowly.
The input circuits of some high speed op amps will sink large
currents to their negative supply during power up and power
down. The Schottky diode at I
OUT
limits any negative-going
transitions to less than -0.4V, avoiding the SCR latchup
which could result if significant current was injected into the
parasitic diode between I
OUT
and DGND of the ICL7121.
This diode is not needed when using the ICL7650 ultra low
V
OS
op amp.
Digital Interface
The ICL7121 has a 16-bit latch onboard and can interface
directly to a 16-bit data bus. As shown in Figure 4, external
latches or peripheral ICs can be used to interface to an 8-bit
data bus. To ensure that the data is written into the onboard
latch, the data must be valid 200ns before the rising edge of
WR. If WR and CS are both low, the onboard latch is
transparent and the input data is directly applied to the
internal R-2R ladder switches. While this simplifies
interfacing in non-microprocessor systems, having WR low
before data is valid may cause additional glitchews in some
microprocessor systems. To avoid these glitches, data must
be valid at the time WR goes low.
All digital interfaces can suffer from capacitive coupling
between the digital lines and the analog section. There are
two general precautions that will reduce this capacitive
coupling problem: 1) reduce stray capacitance between
digital lines and analog lines; and 2) reduce the number of
transitions on the digital inputs. Careful board layout and
shielding can minimize the capacitive coupling (see Figure
5). The activity on the digital input lines can be reduced by
using external latches or peripheral interface ICs between
the microprocessor bus and the ICL7121. This will reduce
the number of transitions on the digital data and control lines
of the ICL7121, thereby reducing the amount of digital noise
coupled into the sensitve analog sections.
0000
0000
0000
0000
0
+V
REF
(1/2
15
)
+V
REF
(1 - 1/2
14
)
+V
REF
(1 - 1/2
15
)
1111
1111
1111
1111
1000
0000
0000
0010
1000
0000
0000
0001
1000
0000
0000
0000
+V
REF
TABLE 1. 2’S COMPLEMENT BIPOLAR OPERATION
DIGITAL INPUT
ANALOG OUTPUT
MSB
LSB
FIGURE 4. INTERFACE TO 8-BIT MICROPROCESSOR
ICL7121
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ICL7121KCJI | 16-Bit Multiplying Microprocessor-Compatible D/A Converter |
| ICL7121LMJI | 16-Bit Multiplying Microprocessor-Compatible D/A Converter |
| ICL7121 | 16-Bit Multiplying Microprocessor-Compatible D/A Converter |
| ICL7121JCJI | 16-Bit Multiplying Microprocessor-Compatible D/A Converter |
| ICL7121JMJI | 16-Bit Multiplying Microprocessor-Compatible D/A Converter |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICL7121LMJI | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| ICL7121M | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Converter IC |
| ICL7126 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:3 1/2 Digit, Low Power, Single Chip A/D Converter |
| ICL7126C/D | 功能描述:顯示驅(qū)動(dòng)器和控制器 RoHS:否 制造商:Panasonic Electronic Components 工作電源電壓:2.7 V to 5.5 V 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-44 封裝:Reel |
| ICL7126CC/D | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Low Power, 3 Digit A/D Converter |
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