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參數(shù)資料
| 型號： | ICL7104-14 |
| 廠商： | Intersil Corporation |
| 英文描述： | 14-BitMicroprocessor-Compatible, 2-Chip, A/D Converter(14位、微處理器兼容的2片A/D轉(zhuǎn)換器) |
| 中文描述： | 14 - BitMicroprocessor兼容，2芯片，A / D轉(zhuǎn)換（14位，微處理器兼容的2片的A / D轉(zhuǎn)換器） |
| 文件頁數(shù)： | 10/21頁 |
| 文件大?。?/td> | 198K |
| 代理商： | ICL7104-14 |
5-15
TABLE 1. DIRECT MODE TIMING REQUIREMENTS
(Note: Not tested in production)
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNIT
t
BEA
XBEN (Min) Pulse Width.
-
300
-
ns
t
DAB
Data Access Time from XBEN.
-
300
-
ns
t
DHB
Data Hold Time from XBEN.
-
200
-
ns
t
CEA
CE/LD Min. Pulse Width.
-
350
-
ns
t
DAC
Data Access Time from CE/LD.
-
350
-
ns
t
DHC
Data Hold Time from CE/LD.
-
280
-
ns
t
CWH
CLOCK 1 High Time.
-
1000
-
ns
TABLE 2. HANDSHAKE TIMING REQUIREMENTS
(Note: Not tested in production)
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNIT
t
MW
Mode Pulse (Min).
-
20
-
ns
t
SM
Mode Pin Set-Up Time.
-
-150
-
ns
t
ME
Mode Pin High to Low Z CE/LD High Delay.
-
200
-
ns
t
MB
Mode Pin High to XBEN Low Z (High) Delay.
-
200
-
ns
t
CEL
Clock 1 High to CE/LD Low Delay.
-
700
-
ns
t
CEH
Clock 1 High to CE/LD High Delay.
-
600
-
ns
t
CBL
Clock 1 High to XBEN Low Delay.
-
900
-
ns
t
CBH
Clock 1 High to XBEN High Delay.
-
700
-
ns
t
CDH
Clock 1 High to Data Enabled Delay.
-
1100
-
ns
t
CDL
Clock 1 Low to Data Disabled Delay.
-
1100
-
ns
t
SS
Send ENABLE Set-Up Time.
-
-350
-
ns
t
CBZ
Clock 1 High to XBEN Disabled Delay.
-
2000
-
ns
t
CEZ
Clock 1 High to CE/LD Disabled Delay.
-
2000
-
ns
t
CWH
Clock 1 High Time.
1250
1000
-
ns
ICL8052/ICL7104, ICL8068/ICL7104
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICL7104-14 WAF | 制造商:Harris Corporation 功能描述: |
| ICL7104-14CDL | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Data Acquisition |
| ICL7104-14CJL | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Data Acquisition |
| ICL7104-14CPL | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:INTERSIL 功能描述:40 PIN DIP IC 制造商:Harris Corporation 功能描述: |
| ICL7104-16CDL | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Data Acquisition |
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