參數(shù)資料
型號: ICE2A765P
英文描述: ?max. Pout=130W. fop=100kHz. Vbreak=650V. TO220?
中文描述: ?最大。噘\u003d 130瓦。紈褲子弟\u003d 100kHz的。 Vbreak \u003d?650V。的TO220?
文件頁數(shù): 12/25頁
文件大?。?/td> 642K
代理商: ICE2A765P
Datasheet
Preliminary Data
12
August 2001
Preliminary Specification
CoolSET
-F2
ICE2A765P
ICE2B765P
Functional Description
Figure 16
Overcurrent Shutdown
3.6
PWM-Latch
The oscillator clock output applies a set pulse to the
PWM-Latch when initiating CoolMOS
conduction.
After setting the PWM-Latch can be reset by the PWM-
OP, the Soft-Start-Comparator, the Current-Limit-
Comparator, Comparator C3 or the Error-Latch of the
Protection Unit. In case of reseting the driver is shut
down immediately.
3.7
Driver
The driver-stage drives the gate of the CoolMOS
and is optimized to minimize EMI and to provide high
circuit efficiency. This is done by reducing the switch on
slope when reaching the CoolMOS
threshold. This is
achieved by a slope control of the rising edge at the
driver
s output (see Figure 17).
Thus the leading switch on spike is minimized. When
CoolMOS
is switched off, the falling shape of the
driver is slowed down when reaching 2V to prevent an
overshoot below ground. Furthermore the driver circuit
is designed to eliminate cross conduction of the output
stage. At voltages below the undervoltage lockout
threshold V
VCCoff
the gate drive is active low.
Figure 17
Gate Rising Slope
3.8
Protection Unit (Auto Restart Mode)
An overload, open loop and overvoltage detection is
integrated within the Protection Unit. These three
failure modes are latched by an Error-Latch. Additional
thermal shutdown is latched by the Error-Latch. In case
of those failure modes the Error-Latch is set after a
blanking time of 5μs and the CoolMOS
is shut down.
That blanking prevents the Error-Latch from distortions
caused by spikes during operation mode.
3.8.1
Overload & Open loop with normal
load
Figure 18 shows the Auto Restart Mode in case of
overload or open loop with normal load. The detection
of open loop or overload is provided by the Comparator
C3, C4 and the AND-gate G2 (see Figure19). The
detection is activated by C4 when the voltage at pin
SoftS exceeds 5.3V. Till this time the IC operates in the
Soft-Start Phase. After this phase the comparator C3
can set the Error-Latch in case of open loop or overload
which leads the feedback voltage V
FB
to exceed the
threshold of 4.8V. After latching VCC decreases till
8.5V and inactivates the IC. At this time the external
Soft-Start capacitor is discharged by the internal
transistor T1 due to Power Down Reset. When the IC
is inactive V
increases till V
= 13.5V by charging
the Capacitor C
VCC
by means of the Start-Up Resistor
R
Start-Up
. Then the Error-Latch is reset by Power Up
Reset and the external Soft-Start capacitor C
Soft-Start
is
charged by the internal pullup resistor R
the Soft-Start Phase which ends when the voltage at
pin SoftS exceeds 5.3V the detection of overload and
open loop by C3 and G2 is inactive. In this way the Start
Up Phase is not detected as an overload.
0,9
0,95
1
1,05
1,1
1,15
1,2
1,25
1,3
0
0,2
0,4
0,6
0,8
1
dV
Sense
1,2
1,4
1,6
1,8
2
with compensation
without compensation
dt
s
V
μ
S
V
V
t
V
Gate
5V
ca. t = 130ns
相關(guān)PDF資料
PDF描述
ICE2B765P ?max. Pout=130W. fop=67kHz. Vbreak=650V. TO220?
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ICE2B265 ?max. Pout=32W. fop=67kHz. Vbreak=650V. DIP8?
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