參數(shù)資料
型號(hào): ICE1PD265G
廠商: INFINEON TECHNOLOGIES AG
元件分類: 基準(zhǔn)電壓源/電流源
英文描述: Power Factor Controller + Cool- MOS: BoostSET IC for High Power Factor and low THD
中文描述: 功率因數(shù)控制器冷馬鞍山:高功率因數(shù),低諧波失真BoostSET集成電路
文件頁(yè)數(shù): 4/16頁(yè)
文件大?。?/td> 79K
代理商: ICE1PD265G
Infineon Technologies
preliminary
ICE1PD265G
Infineon Tech
PCI Group
10.09.01
4
Functional Description
Introduction
Conventional electronic ballasts and switching power supplies are designed with a bridge rectifier
and a bulk capacitor. Their disadvantage is that the circuit draws power from the line when the
instantaneous AC voltage exceeds the capacitors voltage. This occurs near the line voltage peak
and causes a high charge current spike with following characteristics: The apparent power is higher
than the real power that means low power factor condition, the current spikes are non sinusoidal
with a high content of harmonics causing line noise, the rectified voltage depends on load condition
and requires a large bulk capacitor, special efforts in noise suppression are necessary.
With the ICE1PD265G preconverter a sinusoidal current is achieved which varies in direct instanta-
neous proportional to the input voltage half sine wave and so provides a power factor near 1. This is
due to the appearence of almost any complex load like a resistive one at the AC line. The harmonic
distortions are reduced and comply with the IEC555 standard requirements.
IC
Description
The ICE1PD265G contains a wide bandwidth voltage amplifier used in a feedback loop, an overvolt-
age regulator, an one quadrant multiplier with a wide linear operating range, a current sense compa-
rator, a zero current detector, a PWM and logic circuitry, a totem-pole MOSFET driver, an internal
trimmed voltage reference, a restart timer, an undervoltage lockout circuitry and last not least a
CoolMOS transistor.
Voltage Amplifier
With an external capacitor between VSENSE and VAOUT the voltage amplifier forms an integrator.
The integrator monitors the average output voltage over several line cycles. Typically the integrators
bandwidth is set below 20 Hz in order to suppress the 100 Hz ripple of the rectified line voltage. The
voltage amplifier is internally compensated and has a gain bandwidth of 3 MHz and a phase margin
of 80 degrees. The non-inverting input is biased internally at 2.5V. The output is directly connected
to the multiplier input.
The gate drive is disabled when VSENSE voltage is less than 0.2 V or VAOUT voltage is less than
2.2 V.
If the MOSFET is placed nearby the controller switching inteferences have to be taken into account.
The output of the voltage amplifier is designed in a way to minimize these inteferences.
Overvoltage Regulator
Because of the integrators low bandwidth fast changes of the output voltage can’t be regulated
whithin an adequate time. Fast output changes occure during initial start-up, sudden load removal,
or output arcing. While the integrators differential input voltage remains zero during this fast
changes a peak current is flowing through the external capacitor into pin VAOUT. If this current
exceeds an internal defined margin the overvoltage regulator circuitry reduces the multiplier output
voltage. As a result the on time of the MOSFET is reduced.
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