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參數(shù)資料
| 型號(hào)： | IC61C256AH-25NI |
| 英文描述： | 32K x 8 HIGH-SPEED CMOS STATIC RAM |
| 中文描述： | 32K的× 8高速CMOS靜態(tài)RAM |
| 文件頁(yè)數(shù)： | 5/9頁(yè) |
| 文件大?。?/td> | 97K |
| 代理商： | IC61C256AH-25NI |
IC61C256AH
Integrated Circuit Solution Inc.
AHSR010-0D 4/19/2002
5
AC TEST LOADS
Figure 1.
Figure 2.
AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Levels
Output Load
Unit
0V to 3.0V
3 ns
1.5V
See Figures 1 and 2
480
30 pF
Including
jig and
scope
255
OUTPUT
5V
480
5 pF
Including
jig and
scope
255
OUTPUT
5V
READ CYCLE SWITCHING CHARACTERISTICS
(1)
(Over Operating Range)
-10
-12
-15
-20
-25
Symbol
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
(2)
OE
to Low-Z Output
t
HZOE
(2)
OE
to High-Z Output
t
LZCE
(2)
CE
to Low-Z Output
t
HZCE
(2)
CE
to High-Z Output
t
PU
(3)
CE
to Power-Up
t
PD
(3)
CE
to Power-Down
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Read Cycle Time
10
—
12
—
15
—
20
—
25
—
ns
Address Access Time
—
10
—
12
—
15
—
20
—
25
ns
Output Hold Time
2
—
2
—
2
—
2
—
2
—
ns
CE
Access Time
—
10
—
12
—
15
—
20
—
25
ns
OE
Access Time
—
5
—
5
—
7
—
8
—
9
ns
0
—
0
—
0
—
0
—
0
—
ns
—
5
—
6
—
7
—
9
—
10
ns
2
—
3
—
3
—
3
—
3
—
ns
—
5
—
7
—
8
—
9
—
10
ns
0
—
0
—
0
—
0
—
0
—
ns
—
10
—
12
—
15
—
18
—
20
ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V
and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±200 mV from steady-state voltage. Not 100% tested.
3. Not 100% tested.
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